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'high speed data reading'
1999\02\22@134829 by John Waters

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Hi All,

I have a programmable VLSI chip which has some data and address bus
lines with high speed data running on. I want to use the 16F84 to read
the data changing on the data lines. However, the typical cycle time for
each data bit is 139 ns. For 16F84, the operating speed is only 10MHz,
and each instruction cycle takes already 400 ns. It looks to me that the
16F84 is too slow for this application. Could anyone suggest me some
ways to solve the problem?
Thanks in advance.

John

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1999\02\22@135256 by Harrison Cooper

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If you have any sort of control lines indicating that the data is present,
and a clock, maybe use a deep FIFO ?
Depends on if the data is being burst into your other chip, giving you
enough time to read the FIFO with the PIC prior to the next data coming.

1999\02\22@135459 by Dave VanHorn

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>I have a programmable VLSI chip which has some data and address bus
>lines with high speed data running on. I want to use the 16F84 to
read
>the data changing on the data lines. However, the typical cycle time
for
>each data bit is 139 ns. For 16F84, the operating speed is only
10MHz,
>and each instruction cycle takes already 400 ns. It looks to me that
the
>16F84 is too slow for this application. Could anyone suggest me some
>ways to solve the problem?
>Thanks in advance.


Even an 8 MHz AVR is going to have problems with this,
(125nS/instruction) since you will also want to DO something
with/about it.. Maybe a Scenix chip could be used, or plaed inbetween
to condense the data?  Hard to say w/o more detail.

1999\02\23@045219 by Marc

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> I have a programmable VLSI chip which has some data and address bus
> lines with high speed data running on. I want to use the 16F84 to read
> the data changing on the data lines. However, the typical cycle time for
> each data bit is 139 ns. For 16F84, the operating speed is only 10MHz,
> and each instruction cycle takes already 400 ns. It looks to me that the
> 16F84 is too slow for this application. Could anyone suggest me some
> ways to solve the problem?

You should collect the data in hardware (for example into an SRAM, with a
counter controlling the address lines). A CPLD could be used as programmable
pattern detector to find trigger points (eg to start or stop capturing).

The PIC can then control the capture process, and examine the data
afterwards.

When continous realtime operation is required, you should either implement
everything in hardware (for example FPGA or CPLD), or increase the bus
width and process more data at once. With 1-bit wide serial data that is
obviously easy, but with an 8 bit bus there is no spare bus width left at
the PIC (-> use "bigger" CPU).

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