'battery backed RAM'
I was reading last night that RAM is maintained if VDD is at least 1.5V. On
my last 80C188 design I used a NVRAM controller which managed sensing,
RESET, addressing and battery/VDD switch over for the RAM. So I'm familiar
with that but I'm having some problems thinking about battery backed
operation with a PIC.
Let's say that I found a battery controller chip that sensed VDD, worked
with MCLR and switched VDD to battery to maintain the 1.5V needed for RAM.
Here's my question, which I couldn't find the answer to in data sheets,
when MCLR is taken low as in circuit above, what happens to the I/O pins?
If they are output, are they going to still draw current? Something I don't
want because I'm battery powered now, only to save the RAM registers.
There's a initialization table that states the registers aren't affected
using MCLR like this (kind of like sleep mode). If this is the case, the
section on sleep might point me somewhere except my PIC is not really
sleeping, I'm holding it in reset until power is restored.
Does this make any sense? Any suggestions?
According to the datasheets, TIOZ is the time from asserting !MCLR low
to ports going Hi-Z, about 100ns.
Thus the I/O pins go HI-Z and no, they don't sink or source significant
current in this condition, even if their TRIS state is output.
What info do you guys have about Parallax's 8051-like assembler for PICs ?
Is it time-saving ?
How about the final size of the program ?
Also, have any of you heard about embedding JAVA programs in PICs ?
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