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'a mpsim question about the PIC16c71'
2000\02\04@210030 by Martin McCormick

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       I am using the DOS version of mpsim and am writing/testing
code for a PIC16c71.  Obviously, I can simulate the A/D sample process
in mpsim, but my question is whether or not anything bad will happen
if I happen to read the A/D output before initiating a sample?  Right
now, my plan is to use the TMR0 interrupt to cause samples to be taken
8,000 times per second.  If I start a sample as I leave the ISR, it
should be perfectly complete by the time the next ISR rolls around and
I won't need to set up an ISR for the A/D converter.  I will just get
the previous sample results, save them somewhere, and then start a new
sample.  In the real world with a real PIC, my very first run-through
of this routine will mean that I read the output of the A/D converter
before ever having sampled.  I can live with a garbage sample of some
random kind, but I want to be sure that it won't cause the PIC to
hang or do something odd.  If the output register behaves like any
register, I could even stuff a 0x80 in there on initialization so that
there will be what looks like a quiet sample even if a real one hasn't
run yet.  Samples with no input signal should normally show 0x80 and
vary between 0 and 0xFF.

       Thanks.

Martin McCormick

2000\02\05@124255 by Robert Rolf

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Martin McCormick wrote:
>
>         I am using the DOS version of mpsim and am writing/testing
> code for a PIC16c71.  Obviously, I can simulate the A/D sample process
> in mpsim, but my question is whether or not anything bad will happen
> if I happen to read the A/D output before initiating a sample?  Right

You'll read pseudorandom bits (pseudo because they're usually the same
every time you power up).

> now, my plan is to use the TMR0 interrupt to cause samples to be taken
> 8,000 times per second.  If I start a sample as I leave the ISR, it
> should be perfectly complete by the time the next ISR rolls around and
> I won't need to set up an ISR for the A/D converter.  I will just get

Works this way for me.
However, your variable ISR latency
will cause a small jitter which will degrade your accuracy. (Think about
what happens if you sample a sine wave at zero crossing, but move the
sample time. Your A/D value changes quite rapidly, effectively degrading
your resolution). I would suggest programming the CCP2 (if the '71 has one) to trigger
your A/D samples so that you get jitter free sampling, and use the A/D complete flag to
generate the interrupt. You still get your 8kHz rate, but now it's jitter free.
At the very least trigger your A/D at the very start of the ISR so that
subsequent branches in the ISR code don't change the latency to the A/D trigger.

One very useful exercise is to set and clear a spare bit at the beginning
and end of your ISRs. You can then readily see the jitter on a scope both
in pulse width and pulse period (if you put lots of pulses in the sweep you'll
see how the later ones are blurred).

> the previous sample results, save them somewhere, and then start a new
> sample.  In the real world with a real PIC, my very first run-through
> of this routine will mean that I read the output of the A/D converter
> before ever having sampled.  I can live with a garbage sample of some

You could also trigger the A/D as part of your initialization routine (setting
the channel).

> random kind, but I want to be sure that it won't cause the PIC to
> hang or do something odd.  If the output register behaves like any

It won't.

> register, I could even stuff a 0x80 in there on initialization so that

Probably not. Why would they waste the chip real estate with latches from
the data bus? It is most likely R/O but I have never tried it.

> there will be what looks like a quiet sample even if a real one hasn't
> run yet.  Samples with no input signal should normally show 0x80 and

But if you trigger the A/D as part of the initialization, there -would-
be a real sample there.

> vary between 0 and 0xFF.
>
>         Thanks.
>
> Martin McCormick
spam_OUTRobert.RolfTakeThisOuTspamUALberta.ca

2000\02\06@081305 by Martin McCormick

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       Thanks for a very good reply, pointing out some potential
pitfalls and for the suggestions.  This particular project will
capture telephone-grade audio from a communications receiver so the
very important thing will be to be sure and take the sample at exactly
the same period with no possible jitter due to the ISR's possibly
taking different branches from one iteration to the next so your
suggestion to put the start of sample at the beginning is well taken.
That way, I can forget and add code later that might modify the timing
and not hurt a thing.

       Since the TMR0 register has to be stuffed with a count to
keep the samples coming at the right rate and jitter could also be
introduced there, that pretty well dictates that the very first two
things I do in the ISR is to stuff TMR0, save the last digital sample,
and start a new one.  After that, timing is not critical.

       Thanks for the help.  When I do get this working, I will share
ideas with the list or at least explain why it wasn't such a good idea
after all.  It is to be  a fancy recorder that wakes up every time
audio appears on the output of a communications receiver, stores it in
a buffer, and then spits it out to a cheap cassette tape recorder when
the buffer fills.  That's why the jitter factor is important.  Audio
will eventually be recovered from the PCM.  The 16C71 will be the
front end of the system.  The only thing I am wondering about is how
acceptable the audio output will be even with Nyquist filters.  If it
is too gravley sounding, I will have replaced the mechanical inertia
of a cheap tape drive which cuts off up to 1 second of sound while
starting up with audio that is rotten to listen to.  When I am
through, I will have almost reinvented the 8-bit sound card.:-)

       Actually, I expect sound that is a little distorted due to the
eight bit samples and 4-KHZ cutoff, but we aren't talking about
listening to good music.  If speech is still understandable, I will be
satisfied.

Robert Rolf writes:
>You'll read pseudorandom bits (pseudo because they're usually the same
>every time you power up).

2000\02\06@153054 by paulb

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Martin McCormick wrote:

>   Since the TMR0 register has to be stuffed with a count to keep the
> samples coming at the right rate and jitter could also be introduced
> there, that pretty well dictates that the very first two things I do
> in the ISR is to stuff TMR0, ...

 Presumably using no prescaler, and performing an ADDWF on the timer
rather than simply loading a value.  The combination of these two
nicely compensates for interrupt latency.
--
 Cheers,
       Paul B.

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