Working on a VHDL synthesizable model for the PIC (haven't pinned down
any particular one yet..), partly for fun, perhaps for a future FPGA..
(BTW, is there demand for such a beast? Let me know!). The PIC
architecture is gloriously simple and to the point - making my job
straight forward. So, what are the uses of the different clock phases
Q1, Q2, Q3 and Q4? I see that Q1 latches the INSTRUCTION register. I
also notice references to Q2 and the RTCC. Is that it? Any hints?
> Working on a VHDL synthesizable model for the PIC (haven't pinned down
> any particular one yet..), partly for fun, perhaps for a future FPGA..
> (BTW, is there demand for such a beast? Let me know!).
I havn't worked with FPGA enough to know, so maybe you could tell me how
much would it cost for a chip that could synthesize a 16CXX for ICE? I think
many of us would be interested. I am afraid that it would end up costing as
much as a commercial emulator, (small quantities), after spending months
designing & debugging.
> Hello,
>
> Working on a VHDL synthesizable model for the PIC (haven't pinned down
> any particular one yet..), partly for fun, perhaps for a future FPGA..
> (BTW, is there demand for such a beast? Let me know!). The PIC
> architecture is gloriously simple and to the point - making my job
> straight forward. So, what are the uses of the different clock phases
> Q1, Q2, Q3 and Q4? I see that Q1 latches the INSTRUCTION register. I
> also notice references to Q2 and the RTCC. Is that it? Any hints?
>
> tom coonan
> .....Thomas.CoonanKILLspam@spam@Sciatl.com
Would you be up for Verilog? I find Verilog a bit easier/faster to
code/understand.
Once in Verilog, you can run Veri2Vhdl to get into VHDL. I do not know of
any tools which go the other direction.
What tools do you have access to?
You can get the QuickLogic FPGA tools for $99. This is their full tool kit minus
the programming software. Their parts are full auto-place and auto-route with
generally 100% gate utilization (yes, 100% because they have so many routing
resources). The have Verilog synthesis in their package. Also, the parts come in
a variety of speed grades with the fastest being WICKED fast.
Right now, they have 1k/2k/4k/7k/8k parts. By this time next year, they will be
up to 20k gate parts.
> Hello,
>
> Working on a VHDL synthesizable model for the PIC (haven't pinned down
> any particular one yet..), partly for fun, perhaps for a future FPGA..
> (BTW, is there demand for such a beast? Let me know!). The PIC
> architecture is gloriously simple and to the point - making my job
> straight forward. So, what are the uses of the different clock phases
> Q1, Q2, Q3 and Q4? I see that Q1 latches the INSTRUCTION register. I
> also notice references to Q2 and the RTCC. Is that it? Any hints?
>
> tom coonan
> Thomas.CoonanKILLspamSciatl.com
>
Exactly what I've been looking for!
I was thinking of synthesizing a PIC on an FPGA for In-Circuit Emulation
but I don't have the time to do it. You see, with such a core, we could
add several debug features (similar to Motorola's BDM) and design a
full-featured Emulator. If you want, we could work together and design
such an emulator.
I agree with you. Why have the different clock phases?
Joel said:
>I agree with you. Why have the different clock phases?
If you want this "emulator" to interact with the rest of the circuitry and
the world like a real PIC then you better have it do reads and writes on
the same phases of the clock as the real thing. Otherwise you are asking
for trouble. Timing differences between your "emulator" and a real PIC
can and will jump right up and bite you.
> If you want this "emulator" to interact with the rest of the circuitry and
> the world like a real PIC then you better have it do reads and writes on
> the same phases of the clock as the real thing. Otherwise you are asking
> for trouble. Timing differences between your "emulator" and a real PIC
> can and will jump right up and bite you.
That's right! It is very important for emulators to have timing
specifications the same as the real thing. Otherwise, you don't really
emulate. I'm in the 32-bit CPU emulator business.
But the different clock phases in focus here are internal to the PIC.
This was in reply (or rather an affirming remark?) to Thomas Coonan. The
question is raised with regards to the design of the PIC.
In larger (32-bit, 64-bit), such different clock phases may be required
because of several instruction pipeline stages. In the PIC, there are
only 2 instruction pipeline.
What happens during the different clock phases--that's the question.
> Working on a VHDL synthesizable model for the PIC (haven't pinned down
> any particular one yet..), partly for fun, perhaps for a future FPGA..
> (BTW, is there demand for such a beast? Let me know!).
I havn't worked with FPGA enough to know, so maybe you could tell me how
much would it cost for a chip that could synthesize a 16CXX for ICE? I think
many of us would be interested. I am afraid that it would end up costing as
much as a commercial emulator, (small quantities), after spending months
designing & debugging.
Good point: top-end FPGAs with 20000 gates run around 50-100 dollars
each. On the other hand, we are definitely on the downward curve---in
a year or so they probably will be $10: wouldn't it be nice to be able
to have just one FPGA that can be burned to be any 16Cxx or 17Cxx?
just about the only thing that can't be put on an FPGA is the A/D
converter: especially nice is the possibility of trading off
resources: additional logic vs. additional RAM vs. additional ROM.
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