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PICList Thread
'What is OPCODE for TRIS instruction on PIC16C63'
1999\03\24@174703 by Paul Gaastra

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They assure me that a 16C63 has a TRIS instruction but I can't find
it in the data sheet.

My CCS PCM C compiler generates code with what it perports to
be TRIS instructions but I can't verify that they are correct.  The
data sheet in my Microchip book and the one from the Microchip
web site don't mention TRIS except to say "Dont use it"

Can anyone send me the definition of the bit in the TRIS
instruction?

The CCS generated code doesn't work on my RICE17A emulator or
on my EPROM 16C63.  I'm probably doing something else totally
wrong but I would like to rule out a CCS compiler error.

Thanks


Paul Gaastra                              spam_OUTpgaastraTakeThisOuTspamhort.cri.nz
Technology Development Group, Hort Research
Private Bag 3123            phone +64 7 8584745
Hamilton, NEW ZEALAND         fax +64 7 8584705

1999\03\24@180408 by Paul Gaastra

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Oops.

I just did a search of the PDF of the 16c63 from the Microchip web
site and the TRIS instruction IS documented  in the individual
instruction section but not in the summary table at the front so
please ignore my last request.


Paul Gaastra                              .....pgaastraKILLspamspam@spam@hort.cri.nz
Technology Development Group, Hort Research
Private Bag 3123            phone +64 7 8584745
Hamilton, NEW ZEALAND         fax +64 7 8584705

1999\03\25@002029 by Ravi Pailoor

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Instead of using TRIS instruction, after bank switching use the
following instruction

           MOVLW k
           MOVWF PORTX

Regards

Pailoor


Paul Gaastra wrote:

{Quote hidden}

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1999\03\25@035835 by paulb

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Ravi Pailoor wrote:

> Instead of using TRIS instruction, after bank switching use the
> following instruction

>             MOVLW k
>             MOVWF PORTX

 But why use four instructions and make interrupts difficult when
two instructions do the job perfectly?
--
 Cheers,
       Paul B.

1999\03\25@045737 by Quentin

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"Paul B. Webster VK2BZC" wrote:

>   But why use four instructions and make interrupts difficult when
> two instructions do the job perfectly?
> --
Yup, some of you might remember my ranting about it a few weeks ago.
Somebody replied to me that Microchip are not planning to phase out the
TRIS instruction as yet.
So, sleep easy.
:)

Quentin

1999\03\25@100904 by Lawrence Lile

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I can't get TRIS to work right under CCS either.  I got tired of trying to
figure out what is wrong and just drop into assembler and execute TRIS
there.  Klunky, but effective.


{Original Message removed}

1999\03\25@103519 by Ravi Pailoor

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Paul,

Your code

        MOVLW   k
        TRIS    PORTX

works well with the 5X series, but i believe this topic is for 16C63 as
the
subject line indicates.

For the 14 bit core you need to use the following,

        BSF     STATUS,RP0
        MOVLW   k
        MOVWF   PORTX
        BCF     STATUS,RP0

since the TRIS register is in the other bank.

If I understand PICmicro instructions correctly, the TRIS is an
INSTRUCTION
in the 5X series and REGISTER in the 14 and 16 bit cores, hence you need
to
move the configuration bits to the REGISTER for the 14 and 16 bit
micros.

Could somebody correct me if I am wrong.

Thanks

Pailoor

Paul B. Webster VK2BZC wrote:

{Quote hidden}

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1999\03\25@163333 by paulb

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Ravi Pailoor wrote:

>         MOVLW   k
>         TRIS    PORTX
> works well with the 5X series, but I believe this topic is for 16C63
> as the subject line indicates.

 Yep.  It works *real well* for the 16C63 series as well.  In fact, all
experienced programmers know that for *most* purposes, it is still the
*optimum* way of controlling TRIS.

> For the 14 bit core you need to use the following,

 Wrong expression.  Not "need to", but you "may *optionally*" use the
four instruction sequence.  Or you can use BSF or BCF on individual TRIS
bits or IORWF or ANDWF.  It's very versatile *but* some people have
suspicions as to whether these *might* *in some circumstances* "glitch"
like thse operations do when applied to the PORT register.

 And in fact, much of the time all you want to do is set up a TRIS
register to a pre-determined state, so the TRIS instruction is best.

> If I understand PICmicro instructions correctly, the TRIS is an
> INSTRUCTION in the 5X series and REGISTER in the 14 and 16 bit cores,

 Again, the wording is "the TRIS register is accessible only by special
INSTRUCTION in the 5X series but *ALSO* as a *general-purpose* register
in the 14 and 16 bit cores"

 I'm sorry if you are confused, but the fact is Microchip deliberately
set out to confuse you in the documentation.  I surmise it's a very
personal matter regarding some, obviously senior, design engineer within
MC who has a "bee in his bonnet" about this and the rest are simply
forced to play along with the farce.

 It demonstrates insensitivity to the users (designers) but well,
they're a big successful company (with undeniably good products) so they
can *afford* such little eccentricities.
--
 Cheers,
       Paul B.

1999\03\26@023956 by Ravi Pailoor

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Thanks Paul,

I never tried the two instruction method till date since I was going by
the
book. Now I will start using it and save the 2 instruction space.

Being a member of this list has been a great help.

Thanks once again.

Pailoor

Paul B. Webster VK2BZC wrote:

{Quote hidden}

--
================================================
For Embedded Controls Solutions and Custom Designs
------------------------------------------------------------------------
CHIP TECHNOLOGIES - Member, Microchip Consultant Program
Bangalore
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Webpage : http://business.vsnl.com/chiptech ( updated 16th Feb 1999 )
================================================

1999\03\27@212003 by Dwayne Reid

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Take note that TRIS works ONLY on ports RA, RB, RC.  It will NOT work on
ports RD or RE.

Taken from page 157 of Microchip document DS30234D (16C6x family)

TRIS Load TRIS Register
Syntax: [ label] TRIS f
Operands: 5 < f < 7
Operation: (W) --> TRIS register f;
Status Affected: None
Encoding: 00 0000 0110 0fff

Description: The instruction is supported for code compatibility with the
PIC16C5X products.  Since TRIS registers are readable and writable, the user
can directly address them.

dwayne


Dwayne Reid   <@spam@dwaynerKILLspamspamplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
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1999\03\28@091415 by paulb

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Dwayne Reid wrote:

> Take note that TRIS works ONLY on ports RA, RB, RC.  It will NOT work
> on ports RD or RE.

 For that relative minority who use parts which *have* those ports! ;-)

> Taken from page 157 of Microchip document DS30234D (16C6x family)

> Since TRIS registers are readable and writable, the user can directly
> address them.

 And isn't that an example of doublespeak?  (BS)  Should read "the user
can *in*directly address them".  I consider the TRIS instruction direct
access; you simply use it to write W into the register without any
concern regarding RP0, RP1 etc.

 Most applications would spend the vast majority of time in Bank 0,
would they not?  That is after all, where the ports, timers, and many
important control registers are, are they not?  (Just looking at figures
4-7, 4-8 on page 24 of DS30390D).

 Furthermore, there is much to be said for making code which accesses
bank 1 (etc.) "critical" and disabling interrupts during such code, for
a much cleaner (faster) IRQ service.  (Extension: use bank 1 GPRs only
for interrupt service.)

 The TRIS registers have been classed as "unimportant" and I submit
that access to bank 1 is in fact, quite IN-direct.  I think that the
allocation of the TRIS registers in this bank makes for a very pretty
diagram, but is in fact a design bungle.
--
 Cheers,
       Paul B.

1999\03\29@152549 by John Payson

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|  The TRIS registers have been classed as "unimportant" and I submit
|that access to bank 1 is in fact, quite IN-direct.  I think that the
|allocation of the TRIS registers in this bank makes for a very pretty
|diagram, but is in fact a design bungle.

I must admit to being puzzled by Microchip's address allocation deci-
sions over the years.  A lot of things that "look pretty" can end up
being a real pain in the tusch.

Had Microchip made the PORT and TRIS registers globally addressible,
then TRIS could simply have been a macro for "MOVWF %1+8" or whatever
the offset ended up being.  Unfortunately, they didn't.

Worse, they put the PIR register in bank 0 ONLY [PIE is in bank 1],
thus requiring an ISR to save status before determining the cause of
an interrupt.  I have a 16C74 program wherein I'd like very much to
have the PSP interrupt enabled while I handle a timer tick (since my
timer tick is about 100 cycles long and my PSP interrupt could be
short) but the need to save status before identifying the interrupt
source makes that an expensive proposition.

Hopefully the 18Cxx parts will solve much of this silly banking stuff
once and for all.  Too bad the data sheets aren't out yet...

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