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'VHF PLL controlled with PIC'
1998\11\06@204425 by Starfire Zhu

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face
Hi PIClisters,

Does anyone have experience in progamming a PIC to control a MB1511 or
the like? Please shed me a light.

Thanks in advance!
--
               __________________________________________________
               :-))   TEL: 86-756-2236157  2115540   FAX: 2115541
               :-))   Email: spam_OUTzhuxhTakeThisOuTspamcheerful.com      ICQ#:7037093
               ==================================================

1998\11\06@204635 by Dave VanHorn

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> Does anyone have experience in progamming a PIC to control a MB1511 or
> the like? Please shed me a light.
>
> Tha

I did a National LM1501, is that similar?
What's your application?

1998\11\06@221424 by Chris Eddy

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Starfire; (Former anger set aside)

I haven't done a PLL, but may have to on another project soon.  I thought
of coupling a PLL and PIC, but the customer wants an ultra low cost
device.  Would it be possible (possible for sure, practical is the
question) to couple an R2R or other DAC to a variable cap diode in an RF
circuit, then come back through a prescale into the PIC so that the PIC
can monitor frequency.  In this manner, the PIC can take charge of the
many PLL tasks, except for the RF portions.  My application would only
have to account for temp drift, and as such the PLL doesn't have to have
massive performance.I want to give the user easy selection of five major
transmit frequencies without any complex factory tuning.

Starfire Zhu wrote:

{Quote hidden}

1998\11\07@142710 by Norman Gillaspie

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What you want to build is a frequency locked loop. This stabilizes the
oscillator frequency but does not use the loop to clean up the
phase noise.

Wayne Ryder a friend built a General Coverage receiver using this
method. It worked quite well. The key is to make sure that the LO
phase noise is clean enough to meet your requirements.

Norman Gillaspie

> {Original Message removed}

1998\11\07@142715 by Valter Gruntar

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The PLL has to be done on this manner: - the freq. from the oscillator has to
be divided by n module then has to be compared with the known time base. If
the osc. freq. is to hi then you have to decrement voltage on the varicap
diodes in the osc. and vice versa. This can be done this way.

   |      ___                 ___
   |___|     |________|     |_____   time base
   |         ____         ____
   |____|        |____|        |____   osc.freq.from divider
   |      _
   |___| |_________________    out charge
   |_____________   ________
   |_____________|_|________   out discharge


this can be made with PIC like this

out charge------------|>|------
P                               D1        |
I                                             |
C                                           |                            R1
47Kw100K
out discharge---------|<|------|----------|-------/\/\/\/\------------------
to varicap
                                D2        |                |
                                             |                |
                                           ==              <
                                      C1  |                > R2
                                             |                <
                                         GND             |
                                                             == C2
                                                               |
                                                           GND


In the normal state "out charge" is low and "out discharge" is high. In this
situation voltage on C1 and on varicap diodes is stable. If the freq. want to
decrease, PIC has to put on "out charge" the positive pulse and vice versa
(on "out discharge" negative - gnd pulse if needed to decrement voltage -
freq.)
The filter made with C1, C2, R2 has to be calculated for fastest response and
lowest ripple. Take a look at data sheet for CMOS 4046
The freq. from the divider has to be equal as freq. from time base. To get
this you have to divide osc. freq. by modulo "N". With other words, with
modulo "N" you can set the OSC. FREQ.

Hope this help you

Valter


Chris Eddy wrote:

{Quote hidden}

1998\11\07@142748 by Peter L. Peres

picon face
On Fri, 6 Nov 1998, Chris Eddy wrote:

> Starfire; (Former anger set aside)
>
> I haven't done a PLL, but may have to on another project soon.  I thought
> of coupling a PLL and PIC, but the customer wants an ultra low cost
> device.  Would it be possible (possible for sure, practical is the
> question) to couple an R2R or other DAC to a variable cap diode in an RF
> circuit, then come back through a prescale into the PIC so that the PIC
> can monitor frequency.  In this manner, the PIC can take charge of the
> many PLL tasks, except for the RF portions.  My application would only
> have to account for temp drift, and as such the PLL doesn't have to have
> massive performance.I want to give the user easy selection of five major
> transmit frequencies without any complex factory tuning.

I did something with a MC145171, with and without extra UHF prescaler. The
only trick is to clean the data control lines from the PIC to the
PLL/synthesizer of RF if any is present (i.e. use RCs and proper
decoupling on the data lines). If you fail to do this strange errors can
happen sometimes. The PIC and the synth shared the same clock osc. which
was implemented at the Motorola part.

A PIC-only PLL is best done using a PWM ouput from a single pin followed
by a dumb RC low-pass. A transistor (or two) is (are) sometimes used to
chop a 33V voltage for larger tuning ranges (often used in un-syntesized
TVs). Of course the slow output filter must be accounted for in the PLL
loop to prevent instability. PLLs implemented like this with a PIC are
slow reacting as a rule (is there a rule ?).

Peter

1998\11\07@214318 by Russell McMahon

picon face
In the last few months (year?) Elektor magazine published a circuit
of an RF  frequency stabiliser based on a 16C54. (I can probably dig
the article / reference up if required)

The original circuit is meant to prevent drift in a VFO once it has
been manually tuned.
The circuitry could probably be used essentially unaltered for
control of a series of preselected (or remotely input) frequencies.

As I recall the PIC applies error signals to a capacitor via
resistors (simple integrator) which controls a varicap VFO. I think
it had "fast" and "slow" resistors. Presumably these were drive n
either high, low or O/C.
VFO frequency is read by the PIC along the lines of the recently
discussed frequency meter.


   Russell McMahon


From: Chris Eddy <.....ceddyKILLspamspam.....NB.NET>
>I haven't done a PLL, but may have to on another project soon.  I
thought
>of coupling a PLL and PIC, but the customer wants an ultra low cost
>device.  Would it be possible (possible for sure, practical is the
>question) to couple an R2R or other DAC to a variable cap diode in
an RF
>circuit, then come back through a prescale into the PIC so that the
PIC
>can monitor frequency.  In this manner, the PIC can take charge of
the
>many PLL tasks, except for the RF portions.  My application would
only
>have to account for temp drift, and as such the PLL doesn't have to
have
>massive performance.I want to give the user easy selection of five
major
>transmit frequencies without any complex factory tuning.
>
>Starfire Zhu wrote:
>
>> Hi PIClisters,
>>
>> Does anyone have experience in progamming a PIC to control a
MB1511 or
>> the like? Please shed me a light.
>>
>> Thanks in advance!
>> --
>>                 __________________________________________________
>>                 :-))   TEL: 86-756-2236157  2115540   FAX: 2115541
>>                 :-))   Email: EraseMEzhuxhspam_OUTspamTakeThisOuTcheerful.com      ICQ#:7037093
>>                 ==================================================
>

1998\11\07@215728 by Norman Gillaspie

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I would like to see this article as well.

Maybe the author has a website?

Norman

{Quote hidden}

1998\11\08@190037 by Dennis Plunkett

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9/11/'98


Hey Starfiire,

Want to do a PLL, GOOD!


1/      The loop filter is important so spend some time with this.
2/      Spend the money on a good referance you will require 10ppm for VHF.
Nominaly this referance will be 10MHz
3/      Use seperate clock and data lines to the PLL and decouple via RCs to
stop phase noise
4/      Use seperate and well decoupled power supplies for the PLL and PIC
5/      Use one common ground point for both!
6/      Use ground planes!
7/      Keep all leads short to minimise RF currents that may flow!
8/      Try to keep the lock time in the sub 30mS area
9/      Always monitor the lock of the PLL and DON'T attempt to relaod
unless it         is not locked.
10/     Decide if the frequency for the AMRC values are calculated or stored
(Stored via a look up table is easyest, this can be in the FLASH section of
an F84 so that it can be re-programmed)
11/     Get some one with RF experiance to help.
12/     Philips have a good loop filter programme that will save some time
13/     Varil give very good and simple formulee to calculate the values in
thier app notes


Better tell us exactly what you want, from the programming side things are
simple, but the hardware side is not.


Dennis

1998\11\09@100538 by Brian Robinson

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Whoever did the LM1501  - Please post more info!

The 1501 is the National equivalent to the Fujitsu part.  The control
logic is identical;  there is a "detail: regarding the clock that you
have to pay attention to.  There is an app note at the National website
regarding the MB1501 vs. the National LMX1501 series.

I would very much like to know the details on the controller you did for
the National LM1501!  I am an RF engineer,  and I am trying to learn
about PIC's for these types of applications.  I can give you RF-related
info in exchange,  if you need it.

regards
Brian Robinson


-----Original Message-----
From:   PICLIST [KILLspamPICLISTKILLspamspamMITVMA.MIT.EDU]
Sent:   Friday, November 06, 1998 8:45 PM
To:     PICLIST
Subject:        Re: VHF PLL controlled with PIC

> Does anyone have experience in progamming a PIC to control a MB1511 or
> the like? Please shed me a light.
>
> Tha

I did a National LM1501, is that similar?
What's your application?

1998\11\09@103753 by Dave VanHorn

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face
> I would very much like to know the details on the controller you did for
> the National LM1501!  I am an RF engineer,  and I am trying to learn
> about PIC's for these types of applications.  I can give you RF-related
> info in exchange,  if you need it.


I did it in an F84, the logic is pretty straightforward.
For our application, I only needed to tune in 5khz increments through a
fairly narrow range, so we left the R register as a constant, so I
hardcoded it. I was given 16 bits of the BA register as the appropriate
"channel" value. The other 3 bits were constant for our particular app,
so I hardcoded them as well.

Tricky bits: We were controlling the power to the VCO and PLL, and I had
to add a delay for them to power up, since there was a filter cap that
had to get charged.
I was also a little miserable until I realized that I had to insert NOPs
between the bit operations, otherwise the pic would not reliably output
the bits. (Confirmed with scope) :( I dont' have that problem on the AVR
devices.
I notated which NOPs were absolutely required, and which were maybe
required.
It's been suggested to me that the NOPs aren't needed, and that I was
excesively loading the PIC outputs, but IMHO, 1/2" of trace and a single
CMOS load dosen't fall into that category.



My own particular bugaboo is trying to understand the implications of
setting the loop bandwidth inside the anticipated modulation bandwidth..
For example, say FM stereo, I've got a pilot tone at 19 kHz and stereo
subcarrier at 38 kHz.. If I try to set the loop bandwidth higher than
38, say 50kHz, then I may have the charge pump feeding through to the
VCO, since the ref freq CAN'T be set to more than 200 Khz... If I try to
get it down to say 20Hz, (outside the audio band) then the loop filter
components get <<HUGE>>

When you want wideband modulation, and wide deviation, where does your
loop filter go? (Or should I FM the reference frequency instead, which
is a whole 'nother can of worms?)



That being asked, here's my driver for the 1501:
BAREG and BREG hold the tuning data, and TUNEFLAG is cleared when BAREG
and BREG are loaded, prior to calling PLLON.
This is real working code.

;       LE      RA0     Synth control data takes effect on me ________-___
;       Clock   RA1     Data is latched on rising edge        ____-_______
;       Data    RA2     19 bits of synth control data         ___---_________

PLLDELAY equ    20      ; number of 10mS intervals before the PLL becomes stable
                       ;This delay uses SUBSEC, which is 10mS/Count.
                       ;Subsec is dec'd by the 1mS opsys int from the timer.

;*************************************************************
; This routine is called whenever we want the PLL turned on.
; It may already be on and tuned, if so, then we just return.
; Otherwise, we power up and tune it before returning.
;*************************************************************
;
;Check BITFLAGS, if already tuned, then don't bother
;The idea here is that PLLON can be called willy-nilly,
;and it only does something if there's something to be done.
;This saves all the calling routines the trouble of checking
;status before tuning or powering up the VCO.
;Buried underneath this monster is PLLOFF, which turned it off..
;
PLLON:
       bsf     PORTB,4         ;VCO output High (Power control, High=0n)
       btfsc   BITFLAGS,7      ;If ok then exit, otherwise retune
       retlw   0               ;If already tuned then exit

TUNEVCO:
       bcf     PORTB,2         ;Turn off the PA while tuning
       bcf     PORTA,0         ;(LE)   just in case, it's supposed to be low no
w
       bcf     PORTA,1         ;(clock)ditto
       bcf     PORTA,2         ;Take data low (JIC)

       movlw   h'FF'           ;Roughly 255uS
       movwf   TEMP            ;Wait for pll Powerup

PLL_PWR_WAIT:
       decf    TEMP,1          ;
       bnz     PLL_PWR_WAIT    ;

       ;We need to set the R register with the following:
       ;0000001100100000001
       ;Beware, national's program outputs the data in opposite order!
       ;We may have data in BREG, BAREG and AREG that needs to be preserved.
       ;Ideally, one could re-use those locations after programming the N reg.

       ;Set the R register with hardcoded data

       call    BIT_ZERO        ; Brute force.
       call    BIT_ZERO        ; Fast
       call    BIT_ZERO        ; Small
       call    BIT_ZERO        ; Too dumb to fail
       call    BIT_ZERO        ;
       call    BIT_ZERO        ;
       call    BIT_ONE         ;
       call    BIT_ONE         ;
       call    BIT_ZERO        ;
       call    BIT_ZERO        ;
       call    BIT_ONE         ;
       call    BIT_ZERO        ;
       call    BIT_ZERO        ;
       call    BIT_ZERO        ;
       call    BIT_ZERO        ;
       call    BIT_ZERO        ;
       call    BIT_ZERO        ;
       call    BIT_ZERO        ;
       call    BIT_ONE         ;
       call    BIT_LATCH       ;


SENDNREG:;Send a 19 bit data stream from BREG, BAREG, and AREG

       ;The first three are always zero
       call    BIT_ZERO        ; Brute force.
       call    BIT_ZERO        ; Fast
       call    BIT_ZERO        ; Small

       MOVLW   16              ;Set loop counter for 16 bits
       MOVWF   PNTEMP          ;Just borrowing a temp register

BITLOOP:
       RLF     BAREG,1         ;Rotate BAREG left out of (and into) carry
       RLF     BREG,1          ;Rotate BREG left into carry
       BTFSS   STATUS,0        ;Output the value of the carry bit
       goto    BITL_LO         ;

BITL_HI:
       call    BIT_ONE         ;
       goto    BITLOOP_B       ;

BITL_LO:
       call    BIT_ZERO        ;

BITLOOP_B:
       decf    PNTEMP,1        ;
       BNZ     BITLOOP         ;

       call    BIT_LATCH       ;
       bsf     BITFLAGS,7      ;Indicate we are tuned

       ;This makes the data ready for next time
       RLF     BAREG,1         ;Rotate BAREG left out of (and into) carry
       RLF     BREG,1          ;Rotate BREG left into carry

       movlw   PLLDELAY        ;Roughly 200mS
       movwf   SUBSEC          ;Wait for pll lockup

PLLON_WAIT:
       call    TIME            ;PLL Loops wobble, but they don't fall down.
       BNZ     PLLON_WAIT      ;
       return                  ;Now we can play!

PLLOFF:
       ;
       BCF     PORTB,2         ;Force PAOFF if PLL is off.
       BCF     PORTB,4         ;VCO output Low
       bcf     BITFLAGS,7      ;Flag that we are now untuned
       return

;
;*************************************************************
;How we clock bits out to the PLL
;*************************************************************
BIT_ONE:
       bsf     PORTA,2         ;Set data high
       nop                     ;This NOP may be optional
       bsf     PORTA,1         ;Clock high
       nop                     ;This NOP is required by the PIC
       bcf     PORTA,1         ;Clock Low
       return

BIT_ZERO:
       BCF     PORTA,2         ;Set data low
       nop                     ;This NOP may be optional
       bsf     PORTA,1         ;Clock high
       nop                     ;This NOP is required by the PIC
       bcf     PORTA,1         ;Clock Low
       return

BIT_LATCH:
       bcf     PORTA,2         ;Take data low (JIC)
       nop                     ;This NOP may be optional
       bcf     PORTA,1         ;Take clock low (JIC)
       nop                     ;This NOP may be optional
       bsf     PORTA,0         ;Take LE high
       nop                     ;This NOP is required by the PIC
       bcf     PORTA,0         ;Take LE low
       return
;

1998\11\09@115814 by Peter L. Peres

picon face
On Mon, 9 Nov 1998, Dave VanHorn wrote:

> Tricky bits: We were controlling the power to the VCO and PLL, and I had
> to add a delay for them to power up, since there was a filter cap that
> had to get charged.

How did you mute the output during this time ? I used a PIC pin to quench
the synthesizer's oscillator directly during this time through a low Cr
diode.  (the synth could be programmed statically). I also turned PA power
on after the lock flag went on, and off again before changing frequency.

> When you want wideband modulation, and wide deviation, where does your
> loop filter go? (Or should I FM the reference frequency instead, which
> is a whole 'nother can of worms?)

Without being an authority, I'd say leave the reference alone forever ;) I
don't like the idea of modulation running through such a complex device as
the PLL phase comparator output driver (which often contains un-documented
proprietary slope control features)  with more non-linearity points than I
want to know about. I am saying this, while I own and use several TDA7000
series based FM receivers which work on similar principles, hovewer they
were designed for this from scratch, and have no problems whatsoever.

For FM operation, the books say to use a slow PLL loop, at 30Hz or
thereabout. A reasonable loop filter at 30Hz using a single op-amp is very
easy to have. It uses only 2 external components ;) (hint: integrator, and
steal a 1/2Vdd reference from somewhere). Been there.

Peter

1998\11\09@121044 by Dave VanHorn

flavicon
face
> How did you mute the output during this time ? I used a PIC pin to quench
> the synthesizer's oscillator directly during this time through a low Cr
> diode.  (the synth could be programmed statically). I also turned PA power
> on after the lock flag went on, and off again before changing frequency.

I just turned the PA off, it still radiates a few uW, but nothing to
worry about..
I didn't design the loop filter on that one, it took 200mS to lock :(

{Quote hidden}

That's a possibility. I've been sticking to the passive approach, as I'm
still new to this part, and it has to work.. I was looking at 100Hz to
20Hz, but the cap values were looking like 2000-20000uF.. Seems a BIT on
the large side.
I may need to put gain in the loop anyway, I'm having trouble getting
the VCO to slew 4MHz/Volt at 100 Mhz. I can get it in at 80 Mhz, but
that's not going to cut it.  If I have to take the tuning voltage to
10V, I can do it, but that means putting a gain of 2 in the loop. I
suppose that makes the loop filter easier, but I'm really fighting for a
minimum component count. The tuning diode gives me about 2-1 C ratio
over 0-5V. I keep cutting the L back, and I get close, but then it quits
oscillating. There are some grey areas of the VCO chip, but I can't
change it, and I've got all the docs there are.

1998\11\09@195304 by Mike Keitz

picon face
On Mon, 9 Nov 1998 10:33:33 -0500 Dave VanHorn <RemoveMEdvanhornTakeThisOuTspamCEDAR.NET>
writes:

>When you want wideband modulation, and wide deviation, where does your
>loop filter go?

For FM stereo, the best approach is a very small bandwidth, so all
modulation is outside the loop filter bandwidth.  This gives the best FM
with little phase distortion from the PLL fighting the modulation.  It
may take several seconds for the PLL to lock on frequency, but how often
does the frequency of an FM stereo transmitter need to change?

Such a filter can be implemented with a FET-input op-amp and moderately
sized capacitors in the 1-10 uF range.

>(Or should I FM the reference frequency instead, which
>is a whole 'nother can of worms?)

If you need pure wideband modulation and a fast lock time that's the way
to go.  But it is a can of worms.

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1998\11\09@201347 by Dave VanHorn

flavicon
face
> Such a filter can be implemented with a FET-input op-amp and moderately
> sized capacitors in the 1-10 uF range.

Where can I see this implemented.. It sounds too simple, and I think I
have the wrong picture in my head.

> If you need pure wideband modulation and a fast lock time that's the way
> to go.  But it is a can of worms.
>

I think I'll leave the can-opener on the shelf for now :)

1998\11\09@213313 by Dennis Plunkett

flavicon
face
At 20:09 9/11/98 -0500, you wrote:
>> Such a filter can be implemented with a FET-input op-amp and moderately
>> sized capacitors in the 1-10 uF range.
>
>Where can I see this implemented.. It sounds too simple, and I think I
>have the wrong picture in my head.
>
>> If you need pure wideband modulation and a fast lock time that's the way
>> to go.  But it is a can of worms.
>>
>
>I think I'll leave the can-opener on the shelf for now :)
>
>

Yep it's correct, one OPAMP and a handfull of caps and resistors, and that's
nominally it. The OPAMP is simply connected to the P and Q outputs. Often
the OPAMP will drive a small transistor + RC base filter network, as the
narrow pulses from the OPAMP are used to control the VCO, and the filtered
version off the transistor is used to indicate "LOCK"

Take a look at the National synths (Phillips may give the best app notes),
and perhaps the Varil

Can opener is now in the draw :-)

Dennis

1998\11\10@131419 by kfisk

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I missed the beginning of this thread, however I do have some experience in
this subject matter and I would offer the following; Be careful when using
an OP-AMP in your loop filter. Even FET input opamps can have leakage that
undermines the PLL performance.

As a rule of thumb, a discrete solution is usually the best. You can find
references to these solution from both Motorola and National App. notes. I
don't have any URL's handy, but I've seen a couple of good references on the
NET.

Cheer,

Kevin

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