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PICList Thread
'Using RX interrupts with USART on PIC16C63'
1998\11\23@195526 by Ohtsji, Randie

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Hello,

I am once again in the experimenting stage and have run into a wall........

I'm trying to communicate from one PIC16C63 to another PIC16C63 using the
on-board USART with the rx used in interrupt mode.
I'm running a loop where the contents of RAM is displayed on an LCD and the
RX interrupt updates the ram.  I am sending 12 characters every two seconds
and from what I can see, it looks like only the 1st, 3rd, 5th, 7th, 9th,
11th, and 12th characters are received.

I am using a 20MHz oscillator and running at 9600 baud (well actually 9469
baud with BRGH=0).

My ISR is something like:


;----------------------------------------
;RAM defines

       cblock
       rxbuffer:12             ;12 spaces reserved for rx buffer
       counter:1               ;counter for RX_ISR
       endc


;---------------------------------------
       org     0x0000
       goto    start

       org     0x0004
       goto    ISR

;--------------------------------------
;main program

start
       ...                     ;initialization
loop    ....                    ;display contents of rxbuffer on LCD
       goto    loop

;end of main program


;--------------------------------------
ISR
       ....                    ;disable further interrupts and save
registers (w, status, fsr, pclath)
       call    RX_ISR
       ...                     ;restore registers (pclath, fsr, status, w)
       retfie                  ;enable interrupts


;-------------------------------------
RX_ISR
       movlw   rxbuffer                ;set up pointer
       movf    fsr
       movlw   0x0c            ;12 characters
       subwf   counter,w
       btfss   status,z                ;check for zero
       goto    $+2             ;if not zero, skip next line
       clrf    counter         ;reset counter
       movf    counter,w       ;get count
       addwf   fsr             ;point to location
       movf    rcreg,w         ;get character from rx fifo
       movwf   indf            ;store in rx buffer
       incf    counter         ;advance to next RAM location
       return

Any comments are welcome.  Am I missing something?  Should I be handling the
interrupt different.
Oh, I did by the way do the initialization for interrupts on receive (async)
and clear ram contents in the beginning.

Thanks in advance!

Randie
spam_OUTrandie.ohtsjiTakeThisOuTspamglenayre.com

1998\11\23@201021 by Gordon Couger

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You might try putting a little delay between the characters. Or do it quick
and dirty by sending each character twice.

Gordon

Gordon Couger .....gcougerKILLspamspam@spam@couger.com
Owner PRAG-L PRactical AGriculture List  http://www.couger.com/prag-l
Stillwater, OK        405 624-2855   GMT -6:00
{Original Message removed}

1998\11\23@203236 by Ohtsji, Randie

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Is my interrupt routine too long?

9469 baud = 105uSec

20MHz = 50nSec x 4 clock/cycle = 200nSec per cycle

Don't I have 500+ cycles to do stuff before receiving the next bit?

Randie
randie.ohtsjispamKILLspamglenayre.com


> {Original Message removed}

1998\11\23@205604 by Dave VanHorn

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"Ohtsji, Randie" wrote:
>
> Is my interrupt routine too long?
>
> 9469 baud = 105uSec
>
> 20MHz = 50nSec x 4 clock/cycle = 200nSec per cycle
>
> Don't I have 500+ cycles to do stuff before receiving the next bit?
>


5 cycles per uS, and 525 between interrupts. You shouldnt take that long
though, you risk missing the int, and that's a LONG routine!   Isrs
should be short :)

1998\11\23@211331 by brad

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"Ohtsji, Randie" wrote:
>
> Is my interrupt routine too long?
>
> 9469 baud = 105uSec
>
> 20MHz = 50nSec x 4 clock/cycle = 200nSec per cycle
>
> Don't I have 500+ cycles to do stuff before receiving the next bit?
>
> Randie
> .....randie.ohtsjiKILLspamspam.....glenayre.com
>

This is probably way off the mark, but are you sure your sending the
Chars correctly ?
The rx routine looks fine to me. I'm using similar routine on a 16c66 at
8Mhz 9600 baud
with no problems at all.
Have you sniffed the serial line with a PC to ensure all the data is
being transmitted correctly ?


--
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1998\11\23@213100 by Regulus Berdin

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Hi,

"Ohtsji, Randie" wrote:
> ;-------------------------------------
> RX_ISR
>         movlw   rxbuffer                ;set up pointer
>         movf    fsr
This MOVF should be MOVWF

>         btfss   status,z                ;check for zero
>         goto    $+2             ;if not zero, skip next line
>         clrf    counter         ;reset counter
These 3 lines could be written as:
       btfsc   status,z        ;or skpnz
        clrf   counter

Hope this helps.

regards,
Reggie

1998\11\23@213315 by Ohtsji, Randie

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Out of 12 characters, I do properly receive the 1st, 3rd, 5th, 7th, 9th,
11th, and 12th character.
On the scope, transmit looks okay.

On the transmitter side I am doing a routine similar to (just off the top of
my head):

tx_send
       movlw   0x0c            ;12 characters to send
       movwf   txcounter
       movlw   txbuffer                ;set up pointer
       movwf   fsr
tx_out:
       movf    indf,w          ;get character to send
       movwf   txreg
       btfss   pir1,txif               ;check transmit buffer
       goto    $-1             ;wait, transmit buffer not empty yet
       incf    fsr             ;advance pointer to next RAM
       decfsz  txcounter
       goto    tx_out
       return



Randie
randie.ohtsjispamspam_OUTglenayre.com


> {Original Message removed}

1998\11\24@000849 by Kraig Hartley

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Ohtsji, Randie wrote:
{Quote hidden}

I had the same problem until I checked TXSTA,TRMT instead of PIR1,TXIF.

Transmit
       movwf   TXREG
       bsf     STATUS,RP0
txddn   btfss   TXSTA,TRMT
       goto    txddn
       bcf     STATUS,RP0
       return

1998\11\24@025518 by Dr. Imre Bartfai

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Hi,
maybe you do not have the problem I will describe, but I had it: (excerpt
from data sheet):
"Overrun bit OERR has to be cleared in software. This is done by resetting
the receive logic (CREN is cleared and the set). If bit OERR is set,
transfers ... are inhibited, so it is essential to clear error bit OERR if
it is set." It means also "it is essential for the user to read the RCSTA
register before rading RCREG register". After I did everything went o. k.
I hope this helps.
Imre


On Mon, 23 Nov 1998, Ohtsji, Randie wrote:

{Quote hidden}

1998\11\24@121721 by Ohtsji, Randie

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Hi Kraig,

       Yep, finally found that out too, the hard way last night.  I did two
compares, the first one on the TRMT bit in TXSTA register and the second on
the TXIF bit in the PIR1 register.

       I guess you're right, I only need to be concerned about the TRMT bit
and not the TXIF bit, since I am not using interrupts for the transmission.

       Thanks for the help!


Randie
KILLspamrandie.ohtsjiKILLspamspamglenayre.com


> {Original Message removed}

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