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'UART Q: -Reply'
1996\11\15@061447 by ang (Chee Foon Tiang)

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>
>>Also, can anyone suggest a simple protocol data transfer.
>
>[snip]
>
>I would also be interested in a simple "inter-pic" data transfer
>protocol. My needs suggest something capable of 75 to 150 bytes
>of data in a packet, which eliminates the CAN solutions.
>
>Thanks,
>Arvid Jedlicka

   A bit-banged I2C protocol would suffice.
   100kHz and up to 256 bytes with the block read/write transfer.
   On top of that it won't only be "inter-pic" but
   "Inter IC" (IIC, get it?) as well, if you ever plan to hook
   up other devices onto the bus.

Regards,

Peter Tiang
spam_OUTtiangcfoonTakeThisOuTspamhitachi.com.my

1996\11\17@190158 by Steve Hardy

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> From: "Peter Tiang (Chee Foon Tiang)" <.....TIANGCFOONKILLspamspam@spam@HITACHI.COM.MY>
>
> >
> >>Also, can anyone suggest a simple protocol data transfer.
> >
> >[snip]
> [chop]
>     A bit-banged I2C protocol would suffice.
>     100kHz and up to 256 bytes with the block read/write transfer.
>     On top of that it won't only be "inter-pic" but
>     "Inter IC" (IIC, get it?) as well, if you ever plan to hook
>     up other devices onto the bus.

IIC is a good solution.  Be aware that the timing requirements for
the slave device are pretty severe if implementing in software.  This
is because the slave has to respond to the master as the master blasts
out each byte.  The master controls the clock at all times so it can
run as slowly as it likes.  If you are programming the master and the
slave you can use slower rates than the normal 100 or 400kbps.

When implementing IIC in software on the PIC, be really careful that
the output port lines are always loaded with zeros, since you have to
implement an O/C driver by toggling the corresponding TRIS register.
Problems arise if a read-modify-write cycle is applied to the port
(not relating to the two IIC lines).  Typically, this will reset the
IIC bits to ones which is not desirable.  I got caught out with this
one!

Regards,
SJH
Canberra, Australia

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