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PICList Thread
'Static RAM memory retention Circuit'
1999\08\30@133217 by Barry Coram

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1999\08\30@140735 by Wagner Lipnharski

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{Quote hidden}

The problem seems to be that the RAM consumes that much when it is
selected and output is active.  If both pins /CE and /OC are up level,
it should consume very little current.  What happens when you power off
the PIC? it drains down /CE and /OC pins, right? so it selects the chip
and it consumes.

There is a problem also with the RAM /W (write) pin that also goes down
with the PIC powered off.  All those 3 pins should still in up level
when it goes for power backup. Now you need to think a circuit that does
it. Perhaps using a CMOS inverting gates between PIC and the RAM, and
keep this cmos gates with power too, so when PIC powers off those gates
will keep up level at those RAM pins.

You can also try to switch PIC Ground instead +VCC, by this way all PIC
pins will be toward +VCC instead Ground, so keeping those 3 Ram's pins
virtually up during PIC power off. A high value resistor in parallel to
the diode that connects Ram's VCC to PIC's Vcc will ensure a minimum
pullup current through the PIC to Ram's 3 pins.

                100k?
         .------RRRRR------.
         |                 |
+5VCC-----o------>|---------o------|<--------.
         |     diode       |     diode      +
        PIC                |                3V
         |                RAM             Backup
         o                 |              Battery
        / o switch         |                |
          |                |                |
Gnd--------o----------------o----------------'


You will have few problems when returning power to PIC, since it can
drive LOW level to those 3 Ram's pins. The worst problem is the /W pin,
it can write trash into the RAM, but it can be in a specific address,
the one formed by the address pins at the power up, if it is constant,
just avoid to use that address...

Other point is the RAM's +VCC, it really doesn't need full voltage
during the retention mode, lots of them can do it with less than Vcc/2,
what also reduces current.

Poor's man solution.

$$$'s man solution = Take a look at DALLAS http://www.dalsemi.com they
have plenty of smart sockets to convert any SRAM chip into a
NonVolatile... with battery and something more.

1999\08\30@142429 by Wagner Lipnharski

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ooops, wrong circuit at the previous post... I am getting old and dumb,
this one here doesn't need even the resistor to keep PIC +V polarized
and hold /CE /OC and /W at up level while switched off. The Ram chip
will be at 0.7V above ground when PIC is energized, I can't see any
problems, do you?

+5VCC--------o---------------o--------------.
            |               |              |
            |               |              +
           PIC             RAM             3V
            |               |            Backup
            |               |            Battery
   Switch   |               |              |
       /    |    diode 1    |    diode 2   |
Gnd---o/ o---o------|<-------o------>|------'

1999\08\30@150732 by Mike Keitz

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On Mon, 30 Aug 1999 18:08:15 +0100 Barry Coram
<spam_OUTpiclistTakeThisOuTspamBAZCOR.FREE-ONLINE.CO.UK> writes:
>
> I have since found out that these static RAM chips have to be set
> into a 'data retention mode'. Now can somebody please point me in
> the direction of a suitable circuit (simple if possible) which will
> reliably set the RAM chip into this mode on power down?

It isn't really complicated.   The data retention mode is:

CS inactive
All inputs at full CMOS levels
Vdd possibly reduced

First, you need to be sure the CS pin stays high (same voltage as Vdd) so
the chip is inactive.  It's a good idea to set WE high also to reduce the
chance of an accidental write.

This next part is important.  Although the logic states of the other pins
(address, data, OE) doesn't matter, they are still live CMOS inputs.  If
they are not solidy at one logic level or the other (I think the spec is
within 0.2V of the Vdd or ground pin), the chip will draw a relatively
large current.  Usually with the rest of the circuit powered off, it will
hold the pins to ground potential.   The only major problem is getting CS
(and possibly WE) to follow the battery Vdd line.  In a slow circuit you
could use a resistor.  If you need fast access, one of the Dallas or
similar chips integrates the switchover from regular to battery power and
a fast gate to drive CS and hold it to Vdd when the RAM is on battery
power.

Also be sure that your RAM is rated for low, low power battery backup
operation.  Often this means it has two "L"'s in the part number, not
just one.   Get the manufacturer's data to be sure.


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1999\08\30@164108 by Barry Coram

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Thank you Wagner, and thanks again..  '

That works for me. The zeroth element of the RAM is corrupted on restart as
you predicted, but that is OK as I can just use this as a part of the
volatile RAM which I must have anyway, you PIC boys sure do have the
answers!

The backup current is now down to the more reasonable uA level so this is a
100% fix for me.Great :-))

Thanks again.... Barry


{Original Message removed}

1999\08\30@164516 by steveb

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Any (generic) LP RAM parts that I have used have had two low power
modes, one of them only requiring /CS to be held high when Vcc falls
to 3V. That makes it much easier to do battery backup.

I'm not an ASCII artist so I'll try and describe it in words.
The RAM is powered via (schottky) diodes from either the 3V battery
or 5V, depending on which is higher.

The /CS pin has a pullup resistor to the RAM Vcc (Vbat) pin. Also
attached to /CS is the collector of an NPN transistor. The base
of that transistor is tied to the 5V supply through a resistor. The
emitter is connected directly to the output of your PIC, address
decoder or whatever.

When normal system power is present, the transistor will turn on any
time that the emitter is pulled low, pulling the collector down and
selecting the chip. When system power goes away, the base drops to 0V
with the supply so the transistor remains off and the pullup on the
collector holds the /CS pin at Vbat (low power mode).

It's cheap, fast, doesn't cost much noise margin and works with quasi
ports on 8051's.

Steve.
======================================================
Steve Baldwin                Electronic Product Design
TLA Microsystems Ltd         Microcontroller Specialists
PO Box 15-680, New Lynn      http://www.tla.co.nz
Auckland, New Zealand        ph  +64 9 820-2221
email: .....stevebKILLspamspam@spam@tla.co.nz      fax +64 9 820-1929
======================================================

1999\08\31@110051 by Harold Hallikainen

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Check out the Dallas or Maxim DS1210 or Maxim MAX1210.  This chip handles
switching power from the main supply to one of two batteries (I'm using a
capacitor for backup power).  You also route the chip select line thru
the chip.  This disables reads and writes when the main power is gone.

Harold



Harold Hallikainen
haroldspamKILLspamhallikainen.com
Hallikainen & Friends, Inc.
See the FCC Rules at http://hallikainen.com/FccRules and comments filed
in LPFM proceeding at http://hallikainen.com/lpfm

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