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'Receive errors using BRGH=1 in 16C74'
1996\09\05@094028 by Jim Main

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The Microchip errata sheet for the above says not to use BRGH=1 because
of possible receive errors.

For the faster standard baud rates, you don't have a choice however.  I
need to use a baud rate of 57,600 - which is only available with BRGH=1.

I can stand the occasional non-consecutive error (or up to a handful in
a row) by sending a NACK and getting the packet repeated - but not for a
lot of corruption - does anyone know what the nature of the corruption
is, how long it lasts for and what causes it?

Another point - using a clock rate of 16MHz with BRGH=1, the % error in
the book is 1.6%.  What error could be tolerated??


--
Jim

1996\09\05@151922 by Ray Gardiner

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>The Microchip errata sheet for the above says not to use BRGH=1 because
>of possible receive errors.
>
>For the faster standard baud rates, you don't have a choice however.  I
>need to use a baud rate of 57,600 - which is only available with BRGH=1.
>
>I can stand the occasional non-consecutive error (or up to a handful in
>a row) by sending a NACK and getting the packet repeated - but not for a
>lot of corruption - does anyone know what the nature of the corruption
>is, how long it lasts for and what causes it?
>
>Another point - using a clock rate of 16MHz with BRGH=1, the % error in
>the book is 1.6%.  What error could be tolerated??
>

I suspect this is a deep subject, but let me first just skim the surface
with a few observation from my own experience.

The microchip errata is not very specific, it simply says you
**MAY** have problems with errors when BRGH=1.

I have been using BRGH=1 on the 16c74 at 156250 bps without problems.
however I am transmitting short packets with error recovery, so if I
get an ocassional error the transaction is retried. This is not fatal.

Another issue, is that I am communicating with a mitsubishi M37450 and
consequently have complete control over matching baud rates etc. This
is something that might be a problem if your application requires you
to talk to a PC.

Just in the last few weeks I ran some trials with BRGH=0 and BRGH=1
and over millions of packets I could not pick any difference in the
error rate. (This was with short RS485 cabling). If anything the error
rate was slightly higher with BGRH=0. The trials were carried out at
38.4k.

The drop in sampling from x64 to x16, is probably going to make
the system more sensitive to slightly mismatched baudrates. This
is possibly the reason for the reported problems.

                       regards,


Ray Gardiner, 104 Macintosh Street, Shepparton, Victoria 3630,  Australia
spam_OUTrayTakeThisOuTspamnetspace.net.au

1996\09\05@155449 by Alexej Vladimirov

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Hello Jim!

05 Sep 96, .....PICLISTKILLspamspam@spam@MITVMA.MIT.EDU writes to Alexej Vladimirov:

P> does anyone know what the nature of the corruption is, how long it
P> lasts for and what causes it?

I forward my old message from the Microchip BBS.

=== Cut ===
Hello All!

I confirm PIC16C74 SCI hardware bug, described by:
Neilw(04-apr-95), Windels(28-jul-95), JScorse(29-jul-95) and
Dennis Millard(31-jul-95).

We use asynchronous 8-bit mode with following settings:

RCSTA=10010000, what means:         TXSTA=00100100, what means:
SPEN  - Serial port enable          CSRC  - Don't care
RC8/9 - Selects 8-bit reception     TX8/9 - Selects 8-bit transmission
SREN  - Don't care                  TXEN  - Transmit enabled
CREN  - Enables reception           SYNC  - Asynchronous mode
                                   BRGH  - High speed
                                   TXD8  - 9th bit of transmit data
We use Fosc=5 MHz and 9600 desired baud rate.
Calculated value for SPBRG at this conditions is 31.

At this conditions PIC receive with errors (mostly on bit7).
Errors is depended from settings bit SREN, which is defined "don't care".
If bit SREN=1, for codes from 40h to 7Fh, bit7 frequently sets to 1.
              for codes with bit0 set to 1, bit7 also sets to 1.
If bit SREN=0, random errors occurs.
Errors is also depended from SPBRG settings.
If decrease SPBRG value - 30 instead of 31 desired, error probability
decreases and errors from bit0 disappears. Other errors remains.

Test program (loop-back test):

list c=132,p=16c74,r=dec,t=on,x=on,e=1
title "SCI TEST Programm"
#include "p16cxxd.inc"
#include "p16cxx.inc"
; Definition
movlf macro Fil,Lit
movlw Lit
movwf Fil
endm
;
U%mail.ormix.riga.lv
org 0
goto Start
;
U%mail.ormix.riga.lv
org 4
goto 0
;---------------------------------------------------------------
Start
clrwdt
bsf STATUS,RP0
movlf (OPTION_REG&07fh),0ffh
clrf (PIE1&07fh)
clrf (PIE2&07fh)
clrf INTCON
; Set Serial interface
movlf (TXSTA&07fh),10100100b ;SCI 8 bit transmitt async /16
; movlf (SPBRG&07fh),30 ;9600 (10.080645161) Baud
movlf (SPBRG&07fh),31 ;9600 (9.765625) Baud
bcf STATUS,RP0
movlf RCSTA,10110000b ;SCI enable 8 bit receive
Tloop
RxBt
; Wait while RxReg is empty
btfss PIR1,RBFL
goto RxBt
; Receive byte
movfw RCREG
btfss RCSTA,OERR
goto TxBt
bcf RCSTA,CREN
bsf RCSTA,CREN
TxBt
; Wait while TxReg isn't empty
btfss PIR1,TXIF
goto TxBt
; Transmit byte
movwf TXREG
goto Tloop
;
U%mail.ormix.riga.lv
end

Work-around:
At the same circuit we change BRGH=1 to BRGH=0.
Calculated value for SPBRG at this settings is 7.
All works fine.
We check also at 19200 bps (SPBRG=3) and at 38400 bps (SPBRG=1). No errors.

Summary: PIC16C74 SCI mode with BRGH=1 don't work.

We check this bug with PIC16C74/JW crystals with the following marking:
- PIC16C74 ENG SMP 9430 CAT Rev A2
- PIC16C74 ENG SMP 9502 CAT Rev A2
- PIC16C74/JW 9524 SAT
- PIC16C74ME A2 BOND 9443 CAA - Emulator pod

Crystal with the following marking work without this problem:
- PIC16C74/JW 9508 CAT

=== Cut ===

Alexej Vladimirov  avladspamKILLspammail.ormix.riga.lv
http://www.ormix.riga.lv/eng/mchip/mchip.htm
...more than 170 Microchip-related links now...
--- GoldED/2 2.50+

1996\09\25@162933 by Alex I. Torres

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> Summary: PIC16C74 SCI mode with BRGH=1 don't work.
>
> We check this bug with PIC16C74/JW crystals with the
> following marking:
> - PIC16C74 ENG SMP 9430 CAT Rev A2
> - PIC16C74 ENG SMP 9502 CAT Rev A2
> - PIC16C74/JW 9524 SAT
> - PIC16C74ME A2 BOND 9443 CAA
> - Emulator pod
>
> Crystal with the following marking work without this
> problem:
> - PIC16C74/JW 9508 CAT

PIC16C74/JW  9607 SAT alse working.
I have a project with 115.2 bps.

-----------------------------
  Best Wishes, Alex Torres.
  Kharkov, Ukraine, exUSSR.
  E-Mail To : .....altorKILLspamspam.....cook.kharkov.ua   via InterNet
              or 2:461/28             via FidoNet

---GoldED 2.50.A0531+
* Semi-Pruduction-Quality Programmer
* for 16Cxx,24xx,93xx - OK.
* 14000 -implemented but not tested.
* only $40 !
* no external power, MsDos & Windows Software.

1996\09\26@171815 by Jim Main
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In article <EraseME324410cbspam_OUTspamTakeThisOuTf28.n461.z2.fidonet.org>, "Alex I. Torres"
<altorspamspam_OUTCOOK.KHARKOV.UA> writes
> PIC16C74/JW  9607 SAT alse working.
>I have a project with 115.2 bps.

Without any errors at all??

--
Jim Main


'Receive errors using BRGH=1 in 16C74'
1996\10\06@002610 by Alex I. Torres
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>> PIC16C74/JW  9607 SAT alse working.
>> I have a project with 115.2 bps.
>
> Without any errors at all??

Yes, but in my project PIC most time transmitt data,
and receive a command.
This device is a hart rate monitor system (Holter monitoring)
that have 8Mbyte memory  to storage 2 ch. ECG. And then all
memory transmitt into PC.
This work! And one problem - the power supply. Now I use 4 AA
rechargable and 2 MAXims DC-DC converter. And now I try to do
this with 2 AA battaries.

  Best Wishes, Alex Torres.
  Kharkov, Ukraine, exUSSR.
  E-Mail To : @spam@altorKILLspamspamcook.kharkov.ua   via InterNet
              or 2:461/28             via FidoNet

--- GoldED 2.50.A0531+
* Origin: Future Hardware, (0572)32-31-62 (2:461/28)

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