'Re [EE]: Foolproof input line'
|part 1 3747 bytes content-type:text/plain; (decoded 7bit)
> I need simple converting circuit to protect PIC input.
> Input levels 0 - 5v - 12v, open or not collectors.
> Could anybody comment attached .gif, please.
> Isn't it an overkill?
Maybe you should define the criteria a little more tightly and make this a
design challenge :-)
Low 0 - 2v (say) or less
High 4 - 12 (say) or open inputs
Safe or Fails-Safe for input voltages outside these ranges
ALWAYS meets ALL PIC datasheet OPERATING condition specs.
Does not affect power supply in micropower applications.
Would be useful to specify PIC acceptable input voltage range and Vdd used.
Note that, for 5 volts in V at PIC pin = (5-0.6) x 3.3/(3.3+1.2)
= 3.2v into PIC
This is OK for typical PICs which have a Vin_high_min of 2.4 V at Vdd = 5v
BUT would not meet spec for true CMOS inputs on some other devices.
The circuit is more complex than you usually see but the spec is for
*foolproof* and that takes more work than usual. Many circuits are
"designed" on a "near enough is good enough" basis and work almost all of
the time in almost all cases. But are not foolproof. You could get a circuit
with lower parts count by using more complex parts (zener, schottky,
transistor etc). Using just diodes and resistors that circuit is about as
simple as you get while being truly (almost) foolproof. Every component has
a function. Values could be varied. Resistor values are unnecessarily low in
my opinion and could all be increased by a factor of 10. (15k, 12k, 33k).
Call R2/R3 junction point A
Call common point of D1 & D2 anode point B.
Call PIC port pin point C
D2 is interesting as it shows the designer believed the PIC datasheet and
did not wish the PIC input pin to rise (much) above Vcc. When B rises to
5.6v nominal D1 will clamp B by conducting current into Vdd. As shown R3
will conduct (12-5.6)/1.2k = about 5.5mA into Vdd with R values shown and
Vdd MUST be stiff enough to stop this current "pumping" the supply voltage
up. *In a micropower circuit this may not be true*. Increase R's by 10 times
and this becomes about 0.55 mA.
Point C (PIC pin) is ABOUT 0.6v below B due to D2 drop so PIC pin will be at
ABOUT Vdd when circuit is clamped.
To be highly pedantic note that D1 conducts more current than D2 so D2 will
have a slightly lower voltage drop so PIC pin will be SLIGHTLY above Vdd
when in clamping condition. AFAIR PIC spec is for pin not to rise more than
0.2V above Vdd so we would be OK.[[Just checked a random data sheet and
fouind spec was exactly 0 - Vdd. The true pedant will use a Schottky diode
(BAT85 etc) for D1 OR place 2 diodes in series for D2]].[[But it will work
D2 also protects against reverse polarity input.
R2 provides pullup to logic high for open input.
R7 provides ground reference on negative inputs (without it PIC pin floats
except for reverse biased leakage currents in D2.)
I could draw a dozen (+) circuits that would meet this spec but it is
unlikely that any would have a lower parts cost or meet the spec
In a micropower application, removing D2 and adding a 4V7 zener from PIC pin
to ground (Cathode to pin) would prevent Vdd pump up with very low current
drain from Vdd. Note that zener has a soft curve and will clamp to BELOW its
rated voltage for small currents. Placing a 5V1 zener from Vdd to ground
would have the zame effect and would act for multiple input circuits like
this one. Such a zener will still draw some current at 5V and a slightly
higher value may be advisable in very very low power applications (while
still not violating PIC Vdd max OPERATING spec).
part 2 1476 bytes content-type:image/gif; (decode)
part 3 131 bytes
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