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'Re[2]: 17C4X async serial I/O'
1995\10\18@224329 by PETE KLAMMER

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> Date: Wed, 18 Oct 1995 10:37:04 -0700
> From: spam_OUTbbolesTakeThisOuTspamccmail.microchip.com (Brian Boles)
> Subject: Re[2]: 17C4X async serial I/O
>
>      Yes, the term "no relationship" is misleading.  In reality..
>
>      The majority detect acts primarily as a glitch filter.  When it
>      detects a majority of '0' this will be the leading edge of the start
>      bit.  The x16 counter is initialized and starts counting.  When the
>      x16 counter reaches its center, the contents of the majority detect
>      are taken as the bit value, which gives you the 7,8,9 samples.  The
>      circuit will work as in Fig. 13-7.
>
>      As for Fig. 13-4, there IS no connection between start bit detect and
>      majority counter, but what is not shown clearly is the connection
>      between start bit detect and the x16 counter and "clock" signal.  This
>      is how it is done.

So, to put it more accurately (may I put words in your mouth?) there is ``no
relationship'' between the *phase* of the async sampler clock and the leading
edge of the async start bit; in other words, there is 1/16 bit time of
ambiguity in the exact timing of the async bit sampling.

But there definitely ``is relationship'' (stop me if I'm wrong) between the
leading edge of the start bit and the *count* of the  of the async sampler
clock: namely, the async sampler clock is reset when the leading edge is
detected, and from then on, majority-of-three sampling is done approximately
at the middle of each bit.

Actually, I can see how it can be done with just the fast shift register
alluded to.  Why not just describe *exactly* how it is done, instead of the
counter illusion?

>      BTW, this discussion is limited to the 17C4X data sheet, the 16C6X and
>      16C7X data sheets are more accurate on this point.

The illustrations in my 16C6X and 16C7X pages in the 95/96 Data Book don't
even identify the majority circuit, just a box marked ``DATA RECOVERY''.
Nowhere is start-bit detect described or illustrated.

I would like to guess that start-bit detect is triggered whenever the 16-bit
shift register (shifting in from the left) reaches this condition (M=Mark,
the idle line condition; S=Space, the signaling condition; x=don't care, the
noise margin condition, Y=majoritY of three, i.e. S-S-x or S-x-S or x-S-S):

        x x x x x x x Y Y Y x x x x x S
       151413121110 9 8 7 6 5 4 3 2 1 0

In other words, the first space sample I see, which is followed by
majority-of-three space condition at mid-bit, defines a start bit.  Another
possibility is:

        x x x x x x x Y Y Y x x x Y Y Y
       151413121110 9 8 7 6 5 4 3 2 1 0

... in other words, majority-of-three followed a half-bit later by
majority-of-three again.  Which way do you do it?

>      Rgds, Brian.

Peter F. Klammer, Racom Systems Inc.                   .....PKlammerKILLspamspam@spam@ACM.Org
6080 Greenwood Plaza Boulevard                            (303)773-7411
Englewood, CO  80111                                  FAX:(303)771-4708

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