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PICList Thread
'Programmable Logic Questions'
1998\04\27@164222 by Andy Kunz

flavicon
face
Has anybody out there done anything like the following with a single PLD,
or two PLDs?

Inputs:
       Clock
       Data
       Output_Enable
       Count
       Reset

Outputs:
       16-bit counter output (increments on Count pin state change), and reset
to
0x0000 or 0xFFFF when pin Reset is put into a certain state.
       16-bit shift-register output (from Clock/Data transitions)
       NOTE:  All Outputs are Hi-Z or logic depending on state of Output_Enable

At the current time, it doesn't matter to me if the thing is edge- or
level-triggered on the Clock, Count, and Reset pins.  The Clock/Data forms
a serial interface along the lines of SPI or such.

If you've done this or have any related questions, please contact me
PRIVATE at spam_OUTmtdesignTakeThisOuTspamfast.net or .....montanaKILLspamspam@spam@fast.net

I'm interested in knowing what it takes (ie, which vendor, type chip, mode,
etc.), or paying someone who has done it to be able to use it.  I'm just
getting started in more complex PLD's and this seemed like a good place to
ask.  My experience with them to date has been to make address-bus
decoders, basically to make multiple 74-series parts into one chip.

Oh, yes, the obligatory PIC relationship:  It will used to program an
external memory for a PIC17.

Thanks.

Andy

==================================================================
Andy Kunz - Statistical Research, Inc. - Westfield, New Jersey USA
==================================================================

1998\04\27@173514 by )

flavicon
face
Andy Kunz asked:

> Has anybody out there done anything like the following with a single PLD,
> or two PLDs?
>
> Inputs:
>         Clock
>         Data
>         Output_Enable
>         Count
>         Reset
>
> Outputs:
>         16-bit counter output (increments on Count pin state change), and
> reset to
> 0x0000 or 0xFFFF when pin Reset is put into a certain state.
>         16-bit shift-register output (from Clock/Data transitions)
>         NOTE:  All Outputs are Hi-Z or logic depending on state of
> Output_Enable
>
       <Mega Snip>

       For nothing more than for curiosity, wouldn't mind seeing an example
of this myself. All of the examples I've seen use the simple combinational
logic or address decode stuff. I've never had much of a chance to work with
PLD's.

Frank Richterkessing
GE Appliances
frank.richterkessingspamKILLspamappl.ge.com

1998\04\27@194122 by Sean Breheny

face picon face
At 03:45 PM 4/27/98 -0400, you wrote:
>Has anybody out there done anything like the following with a single PLD,
>or two PLDs?
>
>Inputs:
>        Clock
>        Data
>        Output_Enable
>        Count
>        Reset
>
>Outputs:
>        16-bit counter output (increments on Count pin state change), and
reset to
>0x0000 or 0xFFFF when pin Reset is put into a certain state.
>        16-bit shift-register output (from Clock/Data transitions)
>        NOTE:  All Outputs are Hi-Z or logic depending on state of
Output_Enable
<snip>

I have not seen anything like this, but I am curious as to its intended
aplication. If I understand you correctly, you basically want a 16 bit
counter with reset which has simultaneous parallel and serial output.
I must just be missing something, the application is probably obvious :)

Sean


+--------------------------------+
| Sean Breheny                   |
| Amateur Radio Callsign: KA3YXM |
| Electrical Engineering Student |
+--------------------------------+
Fight injustice, please look at
http://homepages.enterprise.net/toolan/joanandrews/

Personal page: http://www.people.cornell.edu/pages/shb7
.....shb7KILLspamspam.....cornell.edu
Phone(USA): (607) 253-0315

1998\04\28@061359 by Andy Kunz

flavicon
face
>I have not seen anything like this, but I am curious as to its intended
>aplication. If I understand you correctly, you basically want a 16 bit
>counter with reset which has simultaneous parallel and serial output.
>I must just be missing something, the application is probably obvious :)

Not quite.

The counter will generate addresses by strobing the Count line.

The Clock/Data will provide the data word to program at this address.

Then I have CE# and WE# brought out to my connection and voila!  Instant
SRAM or FLASH programmer.

Andy

==================================================================
                    Andy Kunz - Montana Design
         Go fast, turn right, and keep the wet side down!
==================================================================

1998\04\28@083045 by Alex Torres
picon face
> From: Andy Kunz <EraseMEmtdesignspam_OUTspamTakeThisOuTFAST.NET>
> Jnls: PICLISTspamspam_OUTMITVMA.MIT.EDU
> Rel`: Programmable Logic Questions
> D`r`: 27 `opek  1998 c. 22:45
>
> Has anybody out there done anything like the following with a single PLD,
> or two PLDs?
>
> Inputs:
>         Clock
>         Data
>         Output_Enable
>         Count
>         Reset
>
> Outputs:
>         16-bit counter output (increments on Count pin state change), and
reset to
> 0x0000 or 0xFFFF when pin Reset is put into a certain state.
>         16-bit shift-register output (from Clock/Data transitions)
>         NOTE:  All Outputs are Hi-Z or logic depending on state of
Output_Enable
>
> At the current time, it doesn't matter to me if the thing is edge- or
> level-triggered on the Clock, Count, and Reset pins.  The Clock/Data
forms
> a serial interface along the lines of SPI or such.

I do the same with Altera MAX7032 (7064). It is very easy to design such
PLD structure in MAX+Plus and programm the chip with ByteBlaster.

Alex Torres, Kharkov, Ukraine (exUSSR)
@spam@altorKILLspamspamgeocities.com
2:461/28 FidoNet
http://www.geocities.com/SiliconValley/Lab/6311

1998\04\28@094525 by Andy Kunz

flavicon
face
>I do the same with Altera MAX7032 (7064). It is very easy to design such
>PLD structure in MAX+Plus and programm the chip with ByteBlaster.

I've received both good an bad comments about MAX+PLUS, and several have
recommended the MAX7032.  Here I thought it was a Maxim part by the name <G>

I've got my Cypress FAE onto this.  Thanks all for the help!

In the words of Arnold, "I'll be back."

Andy


==================================================================
Andy Kunz - Statistical Research, Inc. - Westfield, New Jersey USA
==================================================================

1998\04\28@181707 by Tom Handley

picon face
  Andy, good timing. For the past 3 months I've been spending a lot of time
on my PIC-based logic analyzer. I'm replying here in this list as others are
interested but I'll be glad to discuss the details of your project in
private. Heck, though we have never met I feel like I've known you for
around 3 years ;-)

  Looking at your requirements, you can't fit that design in a typical PLD
such as a 22V10. They are limited to 10 Output Macro Cells (OMC). While the
16-Bit counter is easy the 16-Bit shift register won't fit.

  I've been working with Lattice Semiconductor's ispLSI1016 CPLDs for
around 2.5 years. The device comes in a 44-pin package including PLCC and
TQFP. It provides 32 I/O lines, 4 dedicated inputs, 3 clock lines, and
dedicated In-Circuit-Programming pins. The 80Mhz version sells for around $8
in singles. The software is free. See Hamilton-Hallmark for current pricing.
The general architecture is:

     64 Macrocells.
      2 Megablocks that consist of 8 Generic Logic Blocks (GLB).
     Each GLB supports:
        18 Inputs. 16 global, 2 dedicated.
        20 Product terms (AND gates).
         4 OR gates. 4, 4, 5, 7, Inputs.
         4 configurable D registers (JK and T) with 2-Input XOR gates.
         4 Outputs that can bypass the product terms and registers.
         1 Product term RESET.
         1 Product term clock.
     1 Product term enable for each megablock. (Global for 1016E).
     1 Global RESET.
     3 Global clocks.

  As with any PLD/CPLD/FPGA design there are a lot of trade-offs to be
made. The main thing is a good understanding of the architecture and the
development tools. With your expertise, you should be able to get
`up to speed' fairly quickly. I'll be glad to help. If you are interested,
the following is an overview of Lattice Software tools, and my design.

  Lattice provides a Starter Package that includes the software, books,
interface cable, and an ispLSI2032 sample for around $99. While it's a nice
package, the 2032 is limited compared to the 1016. It is best suited to very
high speed designs. You can order their CD for free and talk to your local
rep to get a 1016 sample. The CD includes data on all of their products but
more importantly, their ISP Synario/ABEL HDL design and Fitter software.
Also included is the ISP download software which takes a JEDEC file and
converts it into an ISP Stream file for ISP programming. There is also
software for their Generic Digital Switches, and C routines to write your
own host ISP download software. This version is restricted to their 44-pin
CPLD devices (1016/E and 2032) but it is very powerful. Other than the
device restrictions, you won't get the Synario timing analyzer, VHDL, and a
few other things. You do get most of Synario which supports both ABEL and a
very nice schematic capture environment. They do include a funtional
waveform tool that is very useful. For more information on Lattice and a
simple schematic of their download cable contact Lattice and my web page at:

     http://www.latticesemi.com
     http://www.teleport.com/~thandley/Wilbure.htm

  I'm using 3 1016s in my design. The first one is a 24-Bit trigger
comparator. It provides a 2-wire serial interface. The host sends 51 Bits of
data. 24 Bits are the trigger bit enables (ie: don't-care Bits). 24 Bits are
the trigger qualifier, and 3 Bits are the post trigger counter delay
selection Bits that did'nt fit in the Control CPLD (an example of
trade-offs...). These 3 Bits connect externally to the Control CPLD. This
CPLD uses 51 shift registers and a 24-Bit comparator with individual
enables. The utilization stats are:

     GLB Utilization (Out of 16):                    93%
     I/O Utilization (Out of 36):                    83%
     Net Utilization (Out of 100):                   85%
     Average Fanout per Net:                         1.34
     Average Inputs per GLB:                         7.27
     Average Outputs per GLB: (all outputs are used) 4.00
     Number of Macrocells:                           60
     Number of GLBs:                                 16
     Number of IOCs (I/Os):                          30
     Number of DIs  (Dedicated Inputs):              0
     Number of GLB Levels (Direct impact on timing): 3

  In this case I was able to utilize most of the CPLD internal resources
and external pins.

  The next chip is the Control block. This selects the clock decade counter
prescaler, /5/4/2 enables, external Intialize, Arm, Stop logic, additional
serial configuration from the trigger comparator block to set up the post
trigger delay count, clock source, and clock polarity select, and the delay
counter which get's it's delay from the trigger comparator block. The stats
are:

     GLB Utilization (Out of 16):                    100%
     I/O Utilization (Out of 36):                    60%
     Net Utilization (Out of 100):                   62%
     Average Fanout per Net:                         2.24
     Average Inputs per GLB:                         8.56
     Average Outputs per GLB:                        3.00
     Number of Macrocells:                           48
     Number of GLBs:                                 16
     Number of IOCs (I/Os):                          18
     Number of DIs  (Dedicated Inputs):              0
     Number of GLB Levels (Direct impact on timing): 4

  This seems to me to point out a `quirk' in the fitter. Notice the GLB
utilization is 100% yet the average outputs per GLB is only 3. Also note
that I have a lot of I/O available. Yet, I've been unable to add even 1
output. In this device I have a variety of logic as well as an 8-Bit shift
register and the delay counter. The delay counter is implemented in ABEL and
provides presets to provide 8 fixed trigger delays. The rest of the logic is
implemented in a `top-level' schematic. I had tried implementing the bulk of
the control logic in an ABEL module but the design would not fit.

  The third chip includes the address counter, address read-back, and SRAM
chip select. This includes a 15-Bit address counter, 15-Bit address
multiplexer, and a simple 4-Bit state machine that enables 4-Bit transfers
between the 4 SRAMs and the address counter. This chip required using all 4
of the dedicated inputs for the state machine and the 32 I/Os for the other
functions. Going back to "trade-offs", I've used every available pin except
the dedicated clocks yet I have a lot of internal resources available.
The stats are:

     GLB Utilization (Out of 16):                    62%
     I/O Utilization (Out of 36):                    100%
     Net Utilization (Out of 100):                   43%
     Average Fanout per Net:                         2.47
     Average Inputs per GLB:                         7.80
     Average Outputs per GLB:                        3.60
     Number of Macrocells:                           36
     Number of GLBs:                                 15
     Number of IOCs (I/Os):                          32
     Number of DIs  (Dedicated Inputs):              4
     Number of GLB Levels (Direct impact on timing): 3

  - Tom

At 03:45 PM 4/27/98 -0400, Andy Kunz wrote:
{Quote hidden}

reset to
>0x0000 or 0xFFFF when pin Reset is put into a certain state.
>        16-bit shift-register output (from Clock/Data transitions)
>        NOTE:  All Outputs are Hi-Z or logic depending on state of
Output_Enable
{Quote hidden}

1998\04\29@101608 by Andy Kunz

flavicon
face
>private. Heck, though we have never met I feel like I've known you for
>around 3 years ;-)

Same here.  Now I find one of our customers in named Tom Handley.  You
don't work for a TV network in NYC, do you?

>   I've been working with Lattice Semiconductor's ispLSI1016 CPLDs for
>around 2.5 years. The device comes in a 44-pin package including PLCC and
>TQFP. It provides 32 I/O lines, 4 dedicated inputs, 3 clock lines, and
>dedicated In-Circuit-Programming pins. The 80Mhz version sells for around $8
>in singles. The software is free. See Hamilton-Hallmark for current pricing.

Sounds pretty close.  The best AMD/Vantis can do so far is $14.00 for a
cross from an Altera EPM7064.  (Somebody has already done it in that based
on my description - it uses 100% internal logic he said).  All I need is 1
real-slow (read "KHz") speed.

I'm going to visit Lattice, I guess.

>   As with any PLD/CPLD/FPGA design there are a lot of trade-offs to be
>made. The main thing is a good understanding of the architecture and the
>development tools. With your expertise, you should be able to get

Er, uh, I only know how to make address decoders right now.  I was reading
through the Cypress stuff, and was pretty much blown away.  A lot of
studying to do.  When I was getting out of college, PAL's were just
becoming available commercially!

>own host ISP download software. This version is restricted to their 44-pin
>CPLD devices (1016/E and 2032) but it is very powerful. Other than the

Guess I have to pay for software for the chip I need, then?

Thanks for the info.

Andy

==================================================================
Andy Kunz - Statistical Research, Inc. - Westfield, New Jersey USA
==================================================================

1998\04\29@110827 by Harrison Cooper

flavicon
face
               A few years ago, Altera was giving out a disk that only
allowed the 7032 (32 macrocells).  I thought I kept them, but since we
had the full development software, it was one of those "erase and use
again" disks.  I'll take a look if anyone is interested in it.  I assume
its public domain since they were passing them out, and now its way old
software. In fact, I would bet (from experience) that none of the files
it creates are compatible with the new release.  But it might be nice to
play with if someone wants to.

                               ----------
                               From:  Andy Kunz
[SMTP:spamBeGonemtdesignspamBeGonespamFAST.NET]
                               Sent:  Wednesday, April 29, 1998 6:53 AM
                               To:  TakeThisOuTPICLISTEraseMEspamspam_OUTMITVMA.MIT.EDU
                               Subject:  Re: Programmable Logic
Questions

                       >private. Heck, though we have never met I feel
like I've known you for
                       >around 3 years ;-)

                       Same here.  Now I find one of our customers in
named Tom Handley.  You
                       don't work for a TV network in NYC, do you?

                       >   I've been working with Lattice
Semiconductor's ispLSI1016 CPLDs for
                       >around 2.5 years. The device comes in a 44-pin
package including PLCC and
                       >TQFP. It provides 32 I/O lines, 4 dedicated
inputs, 3 clock lines, and
                       >dedicated In-Circuit-Programming pins. The
80Mhz version sells for around $8
                       >in singles. The software is free. See
Hamilton-Hallmark for current pricing.

                       Sounds pretty close.  The best AMD/Vantis can do
so far is $14.00 for a
                       cross from an Altera EPM7064.  (Somebody has
already done it in that based
                       on my description - it uses 100% internal logic
he said).  All I need is 1
                       real-slow (read "KHz") speed.

                       I'm going to visit Lattice, I guess.

                       >   As with any PLD/CPLD/FPGA design there are a
lot of trade-offs to be
                       >made. The main thing is a good understanding of
the architecture and the
                       >development tools. With your expertise, you
should be able to get

                       Er, uh, I only know how to make address decoders
right now.  I was reading
                       through the Cypress stuff, and was pretty much
blown away.  A lot of
                       studying to do.  When I was getting out of
college, PAL's were just
                       becoming available commercially!

                       >own host ISP download software. This version is
restricted to their 44-pin
                       >CPLD devices (1016/E and 2032) but it is very
powerful. Other than the

                       Guess I have to pay for software for the chip I
need, then?

                       Thanks for the info.

                       Andy


==================================================================
                       Andy Kunz - Statistical Research, Inc. -
Westfield, New Jersey USA

==================================================================

1998\04\29@120343 by John Lowes

picon face
Andy Kunz wrote:

> I've received both good an bad comments about MAX+PLUS, and several have
> recommended the MAX7032.  Here I thought it was a Maxim part by the name <G>
>

Andy, here are my two cents (rather an buck and a quarter).
I have been using Altera's MAX+PLUS II software for five years and love
it.  If all you need is
a MAX7032 (their smallest part in to 7000 series) then there is a
low-cost (free ?) version available
that only allows AHDL design and programming of 7032's without a
hardware key.  If you require a larger
design, the purchased software will allow fully hierarchical designs
which intermix graphical and
textual input.  I mostly use graphics to define connectivity at the top
page (highest level) and
push into each block which is written in ALtera HDL (AHDL).  AHDL is
easy to learn and is a somewhat
stripped dowm version of VHDL.  It is still very powerful though.
The simulator is one of the best I have ever used, in my opinion. Though
I know people who consider it
to be terrible.  You just have to try it and see.

The main negative response I have heard about MAXPLUS is that it only
works with Altera parts; there
is no intermixing with other vendors.  I understand this viewpoint, but
it's still good software.
Yes, the Data I/O Synario and Aldec Active CAD tools will allow large
multi-part multi-vendor designs,
and are good tools, but the libraries still need to be purchased.  With
MAXPLUS, multi-part systems can be designed and simulated easily, but
you are locked into using Altera parts.
I believe Altera now has 50% or more of the PLD market, so do they need
to worry about who they are
compatible with?

MAXPLUS also still has some memory leak problems which they have never
addressed.  If you're using
the simulator a lot (very large simulations over many hours) and you
notice text and graphics
starting to do wierd things, then shut down and reboot.  In five years,
I can't say I remember ever
having MAXPLUS trash my project.  It is very good about closing files.
Microsoft certainly can't make
this claim!

If you don't get MAXPLUS, I recommend looking at the Aldec EDA tools.
Very easy to use and powerful,
but the simulator isn't as good as Altera's.  It is a more professional
tool, designed with the
ability to easily migrate PLD/FPGA designs to ASICs when the the design
is solid.  I haven't used it
enough to know it inside out and what its bugs are.

Hope this helps.

John

1998\04\29@125743 by Bob Blick

face
flavicon
face
On Wed, 29 Apr 1998, Andy Kunz wrote:
> Sounds pretty close.  The best AMD/Vantis can do so far is $14.00 for a
> cross from an Altera EPM7064.  (Somebody has already done it in that based

An update on the Cypress parts... the 66mhz version of the CY7C371i is in
stock at Marshall for $4.85 in single quantities.

I guess I was remembering pricing on the 128 macrocell 100mhz parts back
when they first came out, this seems a bit more reasonable.

The '371 is the 32 macrocell version of their flash CPLD.

-bob


'Programmable Logic Questions'
1998\05\01@170318 by Tom Handley
picon face
At 08:53 AM 4/29/98 -0400, Andy Kunz wrote:
>>private. Heck, though we have never met I feel like I've known you for
>>around 3 years ;-)
>
>Same here.  Now I find one of our customers in named Tom Handley.  You
>don't work for a TV network in NYC, do you?

  Andy, that's a surprise! Our family sailed to Oregon from England in the
early 1800's and stayed in the Northwest.

>>   As with any PLD/CPLD/FPGA design there are a lot of trade-offs to be
>Er, uh, I only know how to make address decoders right now.  I was reading
>through the Cypress stuff, and was pretty much blown away.  A lot of
>studying to do.  When I was getting out of college, PAL's were just
>becoming available commercially!

  Like other vendors, Lattice's CPLDs are based on a common block, GLB in
this case. It's easy to learn. The Synario software includes a variety of
macros that simplify things. There are macros for counters, decoders,
mux/demux, registers/latches, a variety of arithmetic functions, etc. You
can use these at the schematic level with very little knowledge of the chip.
In the design you mentioned earlier, you can put that down in a few mins not
counting simulation. If you have experience with ABEL, you just add those as
function blocks for the schematic editor. You can take existing ABEL PLD
designs for 22V10s etc, and use them as-is.

>>own host ISP download software. This version is restricted to their 44-pin
>>CPLD devices (1016/E and 2032) but it is very powerful. Other than the
>
>Guess I have to pay for software for the chip I need, then?

  Andy the above devices are 64 and 32 macrocell devices with 32 I/Os,
4 inputs, and clock inputs. Larger devices require the full package which
costs up into the $$$$ range... You can still do a lot with the smaller
devices. In that one design I mentioned earlier, there's a 51-Bit shift
register and a 24-Bit coparator with individual enables. In another chip
I eliminated around 20 74x-family parts.

  - Tom

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