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'Port pin survival question'
1999\01\26@033606 by Rob Santello

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 I need to attenuate the signal from a piezo disc by using a port B pin on
a 16F84.  I want to switch in a resistor (parallel to "ground") by toggling
the port pin between a low out and high Z input. Effectively paralleling
the resistor with the piezo to ground.  The piezo will see some pretty
healthy shocks so it will generate a substantial signal.  The resistor
value looks to be in the neighborhood of 1K or so.  My question is, will
the port pin survive without any additional external protection?

Thanks,
--rob--

1999\01\26@122644 by myke predko

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Hi Rob,

I Would think that a couple of clamping diodes would be all that's
appropriate.  This would use two silicon diodes arranged as:

                  Vcc
                   ^
                   |
                   |
           +--|>|--+
   |       |
PIC |-------+--------------- Piezo Source
   |       |
           +--|<|--+
                   |
                   |
                 -----  Gnd
                  ---
                   -

I know the PICMicro I/O Pins (except for RA4) have these built in, but it
wouldn't hurt having external clamping diodes, especially if you are talking
about high voltages from the Piezo disk.

myke

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1999\01\26@191719 by Dwayne Reid

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Rob wrote:

>  I need to attenuate the signal from a piezo disc by using a port B pin on
>a 16F84.  I want to switch in a resistor (parallel to "ground") by toggling
>the port pin between a low out and high Z input. Effectively paralleling
>the resistor with the piezo to ground.  The piezo will see some pretty
>healthy shocks so it will generate a substantial signal.  The resistor
>value looks to be in the neighborhood of 1K or so.  My question is, will
>the port pin survive without any additional external protection?

Hmm . . .

You need to think this over a bit.  If you use a PIC pin to switch in the
resistor, the protect diodes are going to clamp to about (Gnd-0.6v) and
(Vcc+0.6v).  In other words, the impedance as seen by the piezo is going to
change as the protect diodes conduct.  Is this a problem?

2nd - the current spikes that get routed to the PIC's substrate when those
protect diodes conduct ** MIGHT ** cause anomolies to the PIC's operation.
I'd look for problems in the a/d subsection (if any) as well as possible
program counter type glitches.

I guess it comes down to what you are trying to accomplish.  Why do you need
to change the loading on the piezo?

Note that most any solid state switch is going to have these kinds of
problems.  You may be stuck with a small reed relay.

dwayne


Dwayne Reid   <spam_OUTdwaynerTakeThisOuTspamplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(403) 489-3199 voice     (403) 487-6397 fax

1999\01\27@035252 by Rob Santello

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Dwayne (and all),

Ok, some deeper details (and exposing my ignorance) ...  Currently, the
piezo signal passes through a 47K  and a pair of 1n4148 diodes configured
as both you and Myke suggest before it feeds a non-inverting opamp then
into a buffer opamp and finally into the PIC RB0/INT.  I have 4 available
I/O port A pins that I want to control the sensitivity with.  I am now
using these 4 pins (RA0-RA3) by "switching" in 4 resistors to "ground" on
the the (-) input of the opamp to adjust the gain of that stage.  With 4
pins I get 16 levels.  This works except I can't seem to get acceptable
"even" steps throughout the adjustable range.  The extents are fine but
doesn't seem to be in linear increments.  By experimentation, I found that
placing a 1K resistor across the piezo to ground knocks the signal down so
that I might be able to use it to help get the overall gain where it works
for me.  I would use one of the 4 pins for this resistor and use the
remaining 3 on the opamp as they are.  Since my existing protection diodes
are on the other side of the 47K, I'm not sure how effective they are right
at the piezo where I want to connect this new 1K.  So Dwayne, in answer to
your impedance question, I will try different resistor values until I find
one that works.  Yeah, I'm a bit weak on theory ;-).  So, assuming I can
get this to adjust acceptably for me, how likely is the PIC to survive ...
long term even.

Additionally I've also considered using a digital pot IC but they are
relatively expensive and seem to be hard to get.  I've also thought of
using a par/ser shift register IC like the '595 but can't find one with
open collector outputs.  More levels would be great but this cheap and easy
way should be fine if I can get it dialed in.

Hope this ascii art is sufficient...

                       Vcc
                        |
                        /\  1n4148
                       ----
               47K      |            |\
Piezo |-----/\/\/\/\/\----------------|- \
        |               |            |    \
       /                /\  1n4148   |      \--------------
       \               ----          |      /        |
       /  1K            |            |    /          |
       \               Gnd        ---|+ /            |
       /                          |  |/              |
       \                          |                  |
        |                         |-------/\/\/\/\---|
        |                        /
       PIC                       \
       i/o                       /
       RA0                          \  3 of these to adj gain
                                 /
                                 \
                                  |
                                  |
                                 PIC
                                 i/o
                               RA1-RA3

Thanks guys.
--rob--

{Quote hidden}

1999\01\27@081431 by Thomas McGahee
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----------
> From: Rob Santello <.....rmsanteKILLspamspam@spam@NS.NET>
> To: PICLISTspamKILLspamMITVMA.MIT.EDU
> Subject: Re: Port pin survival question
> Date: Wednesday, January 27, 1999 3:53 AM
>
>

SNIP

{Quote hidden}

Rob,
Try moving the 1K resistor over to the RIGHT HAND side
of the 47K resistor. This will then attenuate the
piezo output by a factor of 47.

Also, I note that in the original diagram you have
the inverting (-) and non-inverting (+) inputs
reversed. I have corrected that on the drawing below:

{Quote hidden}

I hope this helps.
Fr. Tom McGahee

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