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'Philips TV/VCR PLL @ low Fosc anyone ?'
1998\11\13@060938 by Peter L. Peres

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Hello,

 has anyone tried to run a Philips TV/VCR synthesizer chip at a lower
Fosc than specified to obtain lower channel spacing (as required for HF
and other apps) ?

 Are there implications on the I2C timing due to this ?

Peter

1998\11\13@071251 by Bart Stofferis

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Hi Peter,

I used the SDA3302 in a homebuilt 70cm packet radio transceiver.
There is also an equivalent TSA xxxx i can't remember now ...

I2C controlled, 1,2 GHz, very easy to control with a PIC

Bart, ON6HF

{Quote hidden}

1998\11\13@164558 by Mike Morrin

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At 01:01 pm 11/13/98 +0000, Peter L. Peres wrote:
>  has anyone tried to run a Philips TV/VCR synthesizer chip at a lower
>Fosc than specified to obtain lower channel spacing (as required for HF
>and other apps) ?

The problem with these chips is that they are generally single modulus
dividers, so the loop bandwidth must be very low  to get small channel step
size, leading to very slow lock times.

Most communications synthesisers (12.5kHz channel spacing or less) use dual
modulus divider chains to improve the loop bandwidth.  The TV/VCR synth
chips are generally not compatible with dual modulus dividers.  There are a
number of dual modulus compatible synth chips out there (e.g. from Motorola).

For HF work with step size of a few Hz, a fractional N synthesiser is the
way to go.  I am not aware of commercially availble chipsets for fractional N.

regards,

Mike Morrin

1998\11\13@175635 by Brian Robinson

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There are commercially available Fractional-N chips from Texas
Instruments,   and I think that Philips has one now also.

However,  there are lots of potential problems with Fractional N to watch
out for.  If I was building from scratch for HF,  I would use a DDS chip,
probably  followed with some sort of simple PLL for very large frequency
steps, and to clean up the DDS signal.  I believe one or two of the ham
vendors have at least one radio with DDS.

Regards,
Brian Robinson

{Original Message removed}

1998\11\15@111707 by Peter L. Peres

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On Fri, 13 Nov 1998, Bart Stofferis wrote:

> Hi Peter,
>
> I used the SDA3302 in a homebuilt 70cm packet radio transceiver.
> There is also an equivalent TSA xxxx i can't remember now ...
>
> I2C controlled, 1,2 GHz, very easy to control with a PIC

Thanks,

what was your channel pitch ?

Peter

1998\11\15@111716 by Peter L. Peres

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On Fri, 13 Nov 1998, Brian Robinson wrote:

> There are commercially available Fractional-N chips from Texas
> Instruments,   and I think that Philips has one now also.

I don't want fractional N, I'd rather build a straight programmable
divider with a bucketfull of HCTs.

> However, there are lots of potential problems with Fractional N to watch
> out for.  If I was building from scratch for HF, I would use a DDS chip,
>  probably  followed with some sort of simple PLL for very large frequency
> steps, and to clean up the DDS signal.  I believe one or two of the ham
> vendors have at least one radio with DDS.

Yes. Have you noticed the price tag ?

I was thinking of a cheap Philips tuner synth used with a much slower
clock (maybe 100 kHz) and a very slow loop to achieve a very fine channel
pitch. Usually they use 4MHz for a 200 kHz pitch so 100 kHz = 200/40 = 5
kHz which begins to be reasonable. I don't mind using a prescaler with
this setup.

The question was, whether any1 has tried to run the Philips parts this
slow, i.e. whether they are static CMOS, and whether there are nasty
implications on the I2C timing and on the phase comparator outputs (which
usually use some funky proprietary digital PLL algorythms near the lock
point for extra stability etc).

Peter

1998\11\15@141657 by Mike Morrin

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At 06:06 pm 11/15/98 +0000, Peter L. Peres wrote:
>On Fri, 13 Nov 1998, Brian Robinson wrote:
>
>I was thinking of a cheap Philips tuner synth used with a much slower
>clock (maybe 100 kHz) and a very slow loop to achieve a very fine channel
>pitch. Usually they use 4MHz for a 200 kHz pitch so 100 kHz = 200/40 = 5
>kHz which begins to be reasonable. I don't mind using a prescaler with
>this setup.

After my last post, I remembered the REAL problem with the Philips TV tuner
synths when applied to HF applications.

If you look at the block diagram of the chip, you will see that there is a
fixed divide-by-8 prescaler in front of the programmable divider.  This
means that you must run the phase detector and loop 8 x slower than if you
used a synth chip with a direct input to the programmable divider.

regards,

Mike Morrin

1998\11\15@201749 by Norman Gillaspie

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There are also some low cost single chip PLL's used for
shortwave radio and Satellite receiver sound sections.

I beleive there is a Seimens ( there are others) part that some mixers,
2 PLL's and a variable bandwidth FM demod. It looks real interesting.
I think all these had 1Khz tuning steps. I think the shortwave PLL's had
a fine tune cap on the reference to interpolate between steps.

One of the thing to watch out for was the 1khz sampling spurs. They
of course are in the audio band.

If you want to here how bad some of the TV  synthesizers are get a narrow
band FM receiver and if you have a CATV converter box listen to the FM
audio carrier after the signal has been moved to channel 3. It is horriable
The reason they can get away with it on a TV is that they intercarrier
mix down process removes a lot of the phase noise with this process.

Norman


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1998\11\19@095723 by Bart Stofferis

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Hi Peter,

I used the SDA3302 in a homebuilt 70cm packet radio transceiver.
There is also an equivalent TSA xxxx i can't remember now ...

I2C controlled, 1,2 GHz, very easy to control with a PIC

Bart, ON6HF

{Quote hidden}

1998\11\19@095730 by Peter L. Peres

picon face
Hello,

 has anyone tried to run a Philips TV/VCR synthesizer chip at a lower
Fosc than specified to obtain lower channel spacing (as required for HF
and other apps) ?

 Are there implications on the I2C timing due to this ?

Peter

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