Searching \ for 'Phase of internal TMR0 clocking' in subject line. ()
Make payments with PayPal - it's fast, free and secure! Help us get a faster server
FAQ page: www.piclist.com/techref/timers.htm?key=clock
Search entire site for: 'Phase of internal TMR0 clocking'.

Truncated match.
PICList Thread
'Phase of internal TMR0 clocking'
2000\06\02@094240 by Dmitry Kiryashov

flavicon
face
Hi guys.

As it was described in many PIC datasheets (notes A below) two cycles are required
(fetch and execute cycles) to complete any PIC instruction. In fetch cycle PC is
incremented, then instruction is latched. Then in the execution cycle, data memory
is read during Q2 (operand read) and written during Q4 (destination write)

What internal phase (Q1 Q2 Q3 Q4 ???) TMR0 is incremented every cycle. Is it happened
in every Q1 (simultaneously with PC increment) or there is another reason to do it
during other phases of clocking ?

Another question: I still can't understand what was the real reason to introduce
2 clocks delay in TMR0 increment after loading TMR0 with new value.

If someone have discovered those questions and have precise answers please do not
hesitate to share it. Couple of good hints are enough ;)

WBR Dmitry.

-----

Notes A.

The clock input from oscillator is internally divided by four to generate four non-
overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program
counter (PC) is incremented every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4. The instruction is decoded
and executed during the following Q1 through Q4.
.....
A fetch cycle begins with the program counter (PC) incrementing in Q1. In the exe-
cution cycle, the fetched instruction is latched into the "Instruction Register (IR)"
in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4
cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination
write).
.....

2000\06\02@103315 by Scott Dattalo

face
flavicon
face
On Fri, 2 Jun 2000, Dmitry Kiryashov wrote:

> Hi guys.
>
> As it was described in many PIC datasheets (notes A below) two cycles are required
> (fetch and execute cycles) to complete any PIC instruction. In fetch cycle PC is
> incremented, then instruction is latched. Then in the execution cycle, data memory
> is read during Q2 (operand read) and written during Q4 (destination write)
>
> What internal phase (Q1 Q2 Q3 Q4 ???) TMR0 is incremented every cycle. Is it happened
> in every Q1 (simultaneously with PC increment) or there is another reason to do it
> during other phases of clocking ?

According to the C64 data sheet, it's during Q4. Look on page 66 of:

http://www.microchip.com/Download/Lit/PICmicro/16C6X/30234d.pdf

>
> Another question: I still can't understand what was the real reason to introduce
> 2 clocks delay in TMR0 increment after loading TMR0 with new value.

I don't know either. I suspect that there's some kind of pipeline thing that has
to get flushed and updated, but that's just a guess

Scott

2000\06\02@133759 by Dmitry Kiryashov

flavicon
face
Hi Scott.

> > What internal phase (Q1 Q2 Q3 Q4 ???) TMR0 is incremented every cycle. Is it happened
> > in every Q1 (simultaneously with PC increment) or there is another reason to do it
> > during other phases of clocking ?
>
> According to the C64 data sheet, it's during Q4. Look on page 66 of:
>
> http://www.microchip.com/Download/Lit/PICmicro/16C6X/30234d.pdf

Ok. So it means we read _old_ value first then it will be incremented ?

The same clock cycle, Q2 phase we are reading TMR0 value, Q4 phase TMR0 is incremented.
Am I correct ?

WBR Dmitry.

2000\06\02@140526 by Bob Blick

face
flavicon
face
On Fri, 2 Jun 2000, Dmitry Kiryashov wrote:
>
> Ok. So it means we read _old_ value first then it will be incremented ?
>
> The same clock cycle, Q2 phase we are reading TMR0 value, Q4 phase TMR0 is incremented.
> Am I correct ?

Hi Dmitry,
I think so too. Read happens in Q2, increment in Q4.

Cheers,
Bob

2000\06\04@192947 by Tony Nixon

flavicon
picon face
Scott Dattalo wrote:

> > Another question: I still can't understand what was the real reason to introduce
> > 2 clocks delay in TMR0 increment after loading TMR0 with new value.
>
> I don't know either. I suspect that there's some kind of pipeline thing that has
> to get flushed and updated, but that's just a guess

To me it looks like the SYNC circuit takes two cycles to get back in
sync with the internal clock after writing to TMR0. (Another guess)

--
Best regards

Tony

http://www.picnpoke.com
spam_OUTsalesTakeThisOuTspampicnpoke.com

2000\06\05@165148 by Dmitry Kiryashov

flavicon
face
Hi Tony.

Can you explain what do you mean getting back in sync with internal clock ?
Situation is following: prescaler=1, internal osc/4 is used.

WBR Dmitry.

> > > Another question: I still can't understand what was the real reason to introduce
> > > 2 clocks delay in TMR0 increment after loading TMR0 with new value.
> > I don't know either. I suspect that there's some kind of pipeline thing that has
> > to get flushed and updated, but that's just a guess
> To me it looks like the SYNC circuit takes two cycles to get back in
> sync with the internal clock after writing to TMR0. (Another guess)

More... (looser matching)
- Last day of these posts
- In 2000 , 2001 only
- Today
- New search...