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'PLD Question'
1999\08\19@111808 by Andy Kunz

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For a PIC project, I need to make an interface to a PC bus (A0-A15,
handshaking pins, etc) which includes enough registers to create the bus
interface and two FIFOs of about 150-200 bytes each.

Has anybody done anything like this?

Thanks.

Andy

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1999\08\19@112428 by Harrison Cooper

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Probably do it in a FPGA rather than a CPLD.  Large FIFO's eat up CLB's in
them, but there are a few that have ram blocks (like Xilinx spartan series),
and when Phillips was here touting the CoolRunner, I talked with the
designer of the next generation and she was saying they were going to put
RAM blocks as well.  I'm not sure if that part was ever finished, or what
stage since they were bought out by Xilinx.

1999\08\19@185823 by Dennis Plunkett

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At 09:23 19/08/99 -0600, you wrote:
>Probably do it in a FPGA rather than a CPLD.  Large FIFO's eat up CLB's in
>them, but there are a few that have ram blocks (like Xilinx spartan series),
>and when Phillips was here touting the CoolRunner, I talked with the
>designer of the next generation and she was saying they were going to put
>RAM blocks as well.  I'm not sure if that part was ever finished, or what
>stage since they were bought out by Xilinx.
>
>


I would not use an FPGA! infact it is too slow to connect to a PCI bus and
performa all the stuff that you may want (Need more infomation before I can
fully clarify that one) You may bee better off with a GA as they are faster
(Try to get an FPGA to do a SONET interface to a PCI bus!) You may have to
hand craft the thingo to get it to work (FPGA) this will introduce another
set of problems.
As for RAM, YEP can do Look at the ProASIC 500K series from Actel, it has
up to 138kbits (A bit on the taki side as they are a new release). But you
will find that all the manufacturers include embedded logic or RAM.

Dennis

1999\08\19@190654 by Harrison Cooper

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Xilinx has PCI cores.  In fact we have even written our own.  Of course, its
in a virtex part.  He didn't say he wanted the PCI bus, so if running ISA,
it ought to be fast enough.  I'm running 100MHz FIFO's and state machines in
SpartanXL parts right now.



I would not use an FPGA! infact it is too slow to connect to a PCI bus and
performa all the stuff that you may want (Need more infomation before I can
fully clarify that one) You may bee better off with a GA as they are faster
(Try to get an FPGA to do a SONET interface to a PCI bus!) You may have to
hand craft the thingo to get it to work (FPGA) this will introduce another
set of problems.

----- True...cant argue that one!!!

As for RAM, YEP can do Look at the ProASIC 500K series from Actel, it has
up to 138kbits (A bit on the taki side as they are a new release). But you
will find that all the manufacturers include embedded logic or RAM.

Dennis


Good point.  Thats the great thing about this list...we all have our own
experiances and viewpoints, and willing to share them, and allows us to help
make up our mind on how to attack and solve problems.

1999\08\19@193810 by Andy Kunz

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At 05:04 PM 8/19/99 -0600, you wrote:
>Xilinx has PCI cores.  In fact we have even written our own.  Of course, its
>in a virtex part.  He didn't say he wanted the PCI bus, so if running ISA,
>it ought to be fast enough.  I'm running 100MHz FIFO's and state machines in
>SpartanXL parts right now.

I'm using an ISA (PC/104) bus.

Andy

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1999\08\19@205307 by Dennis Plunkett

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At 17:04 19/08/99 -0600, you wrote:
>Xilinx has PCI cores.  In fact we have even written our own.  Of course, its
>in a virtex part.  He didn't say he wanted the PCI bus, so if running ISA,
>it ought to be fast enough.  I'm running 100MHz FIFO's and state machines in
>SpartanXL parts right now.
>
>
Tell me did you use VHDL for this, and if so how did you go with optimising
it for the SPARTTAN part, or did it work first go? Did timming verification
work?

Dennis




{Quote hidden}

1999\08\20@103544 by Tom Handley

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  Andy, I would separate the FIFO's from the CPLD. Otherwise, you will
will have to look at very complex CPLDs or FPGAs as well as very expensive
development tools. Being a `Lattice Semi Guy', I think you could easily do
this in a ispLSI1016E which has 32 I/O's, 64 macrocells, 44-pin PLCC and
smaller packages, and a free six month license for their ispExpert
environment. Xilinx, Altera, and others make similar CPLDs in this range.
All these devices can easily handle an ISA interface.

  Should you decide to go this route with Lattice, let me know...

  - Tom

At 10:29 AM 8/19/99 -0400, Andy Kunz wrote:
{Quote hidden}

------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

1999\08\20@104000 by Harrison Cooper

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on the topic of tools....IF you design in HDL, you can send the files to
Xilinx and they will run it thru thier tools and send back the burn file.  I
wonder if Altera does it?

1999\08\20@105226 by Andy Kunz

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>   Andy, I would separate the FIFO's from the CPLD. Otherwise, you will
>will have to look at very complex CPLDs or FPGAs as well as very expensive

Board space is the problem.  We have two IDT 7201 FIFOs and a GAL22V10 on
it now, and it would sure be nice to get the whole mess into one small
package.  Also simplify the snot out of routing it.

I don't care whose parts get used, so long as it works.  Lattice is a good
choice by me, since they have good local support from the vendor here.

What would it take to convince you to write the logic (I have the 22V20
source I can send you).

Andy

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1999\08\21@184946 by Tom Handley

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  Andy, again the problem is implementing the FIFO. The ISA interface and
FIFO control is trivial. Since you already have the design in 2 FIFO's and a
22V10, moving the FIFO to a CPLD would dramatically raise the cost and it
would require a large device due to the number of internal registers needed.
Lattice and others have devices with internal FIFO's but they are very
expensive and large, typically over 200 pins in xQFP packages. When
designing custom chips there is always a `battle' between internal resources
and available I/O. In the above case, you would be using a large portion of
the internal resources and a small fraction of the I/O but you will be
paying for it...

  Without knowing the details of the design, I would take a hard look at
how large a FIFO you really need. For example 16 Bytes could easily fit in a
smaller CPLD.

  I'll admit I haven't thought this through but I was thinking of using
external logic to control a dual-port SRAM. In this case, you are just
implementing a dual FIFO with the advantage of using one chip for data
storage. There is a suitable Lattice CPLD that comes in a 68-pin PLCC or
100-pin TQFP (14mm x 14mm) package. This would cut board `real-estate' by
more than half but it might increase the cost...

  Believe me, I could use the work right now but unless board space is
`mission critical' compared to cost, I think the existing design is more
cost-effective depending on how much you are paying for the 7201s.

  - Tom

At 10:43 AM 8/20/99 -0400, Andy Kunz wrote:
{Quote hidden}

------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

1999\08\22@181810 by Dennis Plunkett

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At 15:44 21/08/99 -0700, you wrote:
{Quote hidden}

I could not agree more. The problem with the high end FPGAs is size, it
seems that the manufactures in order to keep things as generic as possible
make the thing quite large with lotsa IO, CLBS and that sort of stuff.
Fortunatly they have seen the light and are now offering a bit more of
fixed type stuff in the FPGAs (See paper delivered to the Custom
intergrated circut conference in San Diego this year by the University of
London and Averio) This basicaly requests that some special functions be
placed into these etc.



Dennis



{Quote hidden}

1999\08\23@102326 by Andy Kunz

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>   Without knowing the details of the design, I would take a hard look at
>how large a FIFO you really need. For example 16 Bytes could easily fit in a
>smaller CPLD.

16 bytes each direction would be the bare minimum.  64 would be more
reasonable.  I only use 150 of the 256 most of the time right now.

>   Believe me, I could use the work right now but unless board space is
>`mission critical' compared to cost, I think the existing design is more
>cost-effective depending on how much you are paying for the 7201s.

It's a layout problem.  Half the board space (2-sided) goes to routing the
traces between the two FIFOS, PIC, and PC/104 bus.  The chips use only a
small fraction of that area.

Andy

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