'PICs and battery-backup SRAM'
I've got an application where I want to use a large capacity, low power
SRAM along with a PIC controller. The SRAM will be used to hold data
and I want to use battery backup to protect the contents of the SRAM,
should someone accidentally disconnect the power supply from the circuit
Can somebody help me with 2 questions?
1. What circuitry is necessary to implement battery backup for an SRAM?
2. If the PIC is writing to SRAM when the power goes off, how do I
ensure that invalid data isn't advertently written to the SRAM?
I am using PIC I/O lines to directly control the address/data/control
lines of the SRAM.
Thanks for your help!
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|Hi, I did this recently. I used an ICL7673 from Harris (if memory is
correct) to switch the Vcc for the SRAM between the PIC supply and the
backup battery. It selects the greater of two input voltages and
directs it to SRAM Vcc.
The CS\ of the SRAM has to be tied up to it's Vcc. That way when the
power is off it is still unselected by battery power. Unfortunately, if
a PIC pin is controlling the SRAM cs\ directly, then when the PIC's
power is off, battery power is drained through the PIC's internal
protection diodes. I used a mosfet (can't remember how exactly) so
that battery current wouldn't leak through cs\ pull-up and through PIC
This should isolate the SRAM from the PIC. I used Hitachi
something-something-256 but it had "SLP" or "ULP" markings (for
super/ultra low power). I used 2032 lithium coin cell and the only time
it drained was when I accidentally short circuited it.
I didn't bother with data getting corrupted because it powered itself
down so can't suggest anything from experience here. :)
Gary Patterson wrote:
|Dallas Semiconductor is the primary supplier of chips and intellegent sockets an
d battery-RAM modules. These devices control the power, chip select and write l
ines of static ram, and provide power from a backup battery, and can also contro
l the switching from the main power to backup power without losing data in the s
tatic ram. See this link for more info. Other companies make power control chi
ps. These devices work better and are cheaper most any circuit you can make you
rself. The 'battery socket' devices are neat (you supply your own RAM chip, up
As far as keeping data integrity while writing, and while power is failing, a go
od way is to use a big enough capacitor across the 5 volts, and monitor the powe
r with the PIC. Check if you have over 4.8 volts, then do one short static RAM
operation (write one byte, or shift one byte to serial eEPROMs). If the power fa
ils, it cannot drop fast enough to corrupt the operation because of the power su
pplied by the capacitor.
You can use logical methods to make sure you never read data corrupted by a powe
You can write a 'note' into the ram that you are going to do a write to a certai
n address block, then write the address, then erase the 'note". When you boot u
p, always check for the note, and you will know if an operation stopped in the m
iddle. In addition, take each block of data (perhaps each 256 bytes) and add up
the data to form a 16-bit checksum, which you also write into the RAM. Test th
e checksums when you boot up, and you will likely detect any data corruption. Y
ou can also write redundant blocks in two separate writes, say write data, data
again. Both blocks should have checksums. Later if block 1 reads bad, read bl
ock 2. If block 1 is good, then re-use block 2 the next time you write.
At 02:33 PM 7/8/98 PDT, you wrote:
|Since the original poster said the battery would be used "in case someone
accidentally disconnected the power," long periods of battery operation
are unlikely. I'd be tempted to connect the PIC to the battery supply as
well and make it SLEEP while the power is off. If both the PIC and SRAM
will operate over a range of 3-5.5V, just use diodes to route in either
battery or main power. You'll need a voltage detector connected to a
port to tell when to go to sleep.
Holding the PIC idle by holding MCLR low won't work because the
oscillator will stay on and use a lot of current from the battery. If
you connect the voltage detector to RB0/INT, it can wake the PIC up with
an interrupt when power comes back on. But you probably want to poll the
detector with software to decide when to sleep so a RAM write isn't
Also put a pull-up resistor on the CS pin to be sure the RAM is not
activated when the PIC ports are forced to input during a reset. Coming
out of reset, be sure the software writes the pin to 1 before making it
On Wed, 8 Jul 1998 17:31:18 -0700 Ron Fial <FIAL.COM> writes: ron
>Dallas Semiconductor is the primary supplier of chips and intellegent
>sockets and battery-RAM modules. These devices control the power,
>chip select and write lines of static ram, and provide power from a
>backup battery, and can also control the switching from the main power
>to backup power without losing data in the static ram.
I agree with Ron, the Dallas chips especially are really "trick". They
integrate the voltage detection, power switching, and forcing the chip
select idle. The only real reason not to use one is if you can't afford
If you want to go with a rock-cheap implementation and must cut power to
the PIC, be prepeared for some headaches. Here's a few hints. Some
SRAM's (64K bit and 1M bit) have an active-high chip select pin which can
be used to force the SRAM inactive without messing with the other chip
The active-low chip select can be isolated with a transistor (NPN) or
FET. The collector or drain goes to the RAM chip select, also to a
pull-up resistor to battery backed Vdd. The base or gate goes to
non-batery Vdd. If it's a bipolar a beas resistor is needed. The
emitter or source goes to the PIC output. If power is on, when the PIC
pin goes low, the transistor turns on and pulls the RAM pin low. If
power is off, the transistor can't come on so it is OK for the PIC pin to
>As far as keeping data integrity while writing, and while power is
>failing, a good way is to use a big enough capacitor across the 5
>volts, and monitor the power with the PIC. Check if you have over 4.8
>volts, then do one short static RAM operation (write one byte, or
>shift one byte to serial eEPROMs). If the power fails, it cannot drop
>fast enough to corrupt the operation because of the power supplied by
This is a sound practice. Since RAM writing is so fast, the "big
capacitor" doesn't need to be very big at all. I don't think more exotic
methods will be needed unless the structure of the data requires writing
a large number of bytes to accomplish each update.
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