Post by thread:PIC16C5X PC increment

Hi! I think there is a mistake on the funcional description of the PIC16C5X Serie about the PC increment operation, after the execution of each instruction. On page 1-8 of the Microchip Databook, it says explicitly: "During program execution [PC] is autoincremented with each instruction unless the result of that instruction changes the PC itself: a) ... b) ... c) ... d) If PC is the destination in any instruction (e.g MOVWF 2, ADDWF 2, or BSF 2,5) then the computed 8-bit result will be loaded into the low 8-bits of the PC (...)" I thought case d) was one of the cases PC is not incremented, because "the result of that instruction changes the PC itself". However, executing simulations of several programs (some of them included in application notes), the PC is incremented in those cases (namely, after the instruction ADDWF 2,1 for example). Are the simulators not correct or there is, in fact, a mistake in the description ? Thanks in advance. - Nuno Marques

Nuno Alexandre Marques <spam_OUTnacmTakeThisOuTELVIS.INESC.PT> wrote: > On page 1-8 of the Microchip Databook, it says explicitly: > > "During program execution [PC] is autoincremented with each > instruction unless the result of that instruction changes the PC > itself: > .... > d) If PC is the destination in any instruction (e.g MOVWF 2, ADDWF > 2, or BSF 2,5) then the computed 8-bit result will be loaded into > the low 8-bits of the PC (...)" > > I thought case d) was one of the cases PC is not incremented, > because "the result of that instruction changes the PC itself". However, > executing simulations of several programs (some of them included in > application notes), the PC is incremented in those cases (namely, > after the instruction ADDWF 2,1 for example). > > Are the simulators not correct or there is, in fact, a mistake in > the description ? Nuno: It's a mistake in the documentation. The data book SHOULD say that the PC is always incremented, and that instructions that modify the PC will act on the NEW value. For example, look at the following code: MOVLW 2 ADDWF PC RETLW 100 RETLW 101 RETLW 102 When the ADDWF PC is executed, the first thing that happens is that the PC is incremented (so it now points to the "RETLW 100". Then the contents of the W-register (2) are added to the PC, so it'll point to the "RETLW 102". Finally, the RETLW 102 is executed, so the PIC will return from the subroutine with W = 102. -Andy Andrew Warren - .....fastfwdKILLspam@spam@ix.netcom.com Fast Forward Engineering, Vista, California http://www.geopages.com/SiliconValley/2499

In responce to this question ... {Quote hidden}> Hi! > I think there is a mistake on the funcional description of the PIC16C5X >Serie about the PC increment operation, after the execution of each >instruction. > On page 1-8 of the Microchip Databook, it says explicitly: > > "During program execution [PC] is autoincremented with each instruction >unless the result of that instruction changes the PC itself: > a) ... > b) ... > c) ... > d) If PC is the destination in any instruction (e.g MOVWF 2, ADDWF 2, or >BSF 2,5) then the computed 8-bit result will be loaded into the low >8-bits of the PC (...)" > > I thought case d) was one of the cases PC is not incremented, because >"the result of that instruction changes the PC itself". However, >executing simulations of several programs (some of them included in >application notes), the PC is incremented in those cases (namely, after >the instruction ADDWF 2,1 for example). > Being quite new to the PIC but having investigated numerous Von Neuman and Harvard architectures there seems nothing strange or obviously wrong with the PC being incremented when ever an instruction is fetched.. In fact you see the PC is incremented before instruction execution - i.e. following the instruction fetch. A typical fetch cycle for any processor follows the standard.. Program Counter to Memory Buffer Registers Read Memory for that location (i.e. read the instruction ) Put result of read into the processor Instruction Register. Program Counter to Program Counter + 1. The execution cycle for the instruction, since this PIC has a RISC set no further memory access will be needed, will then modify the registers etc as necessary. If the Program Count to Program Count + 1 action in the fetch did not happen on every fetch, the instruction itself would need to have the address of the next instruction to execute. The much more interesting ideas on this topic are to be found in CISC based systems with pipe line pre-fetch such as the 80x86. The advances in P5 and P6 try to be too clever in my view... Any Comments ... ---------------------------------------------------------------------------- ---------- Tony Grimer ---- cm1918KILLspamscitsc.wlv.ac.uk (Tony D. Grimer) School of Computing (SCIT) Room MC108 Tel - 0902-322764. ---------------------------------------------------------------------------- ----------