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'PIC GPIO and startup.'
2008\02\20@192734 by Clint Sharp

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Using a  logic level MOSFET driven from a PIC 12F GPIO pin, is the fact
that the TRISIO register is set for input at power up sufficient to stop
random triggering  or should I be looking at some kind of
buffer/interlock between the PIC IO pin and the MOSFET?
--
Clint Sharp

2008\02\20@194332 by David VanHorn

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On Wed, Feb 20, 2008 at 7:27 PM, Clint Sharp <spam_OUTpiclistTakeThisOuTspammit.edu> wrote:
> Using a  logic level MOSFET driven from a PIC 12F GPIO pin, is the fact
>  that the TRISIO register is set for input at power up sufficient to stop
>  random triggering  or should I be looking at some kind of
>  buffer/interlock between the PIC IO pin and the MOSFET?

Normallly, you'd use resistors to pull those lines to a defined state
while the uP is in reset or getting initialized. Otherwise, who knows
what happens?

2008\02\20@210527 by Apptech

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>> Using a  logic level MOSFET driven from a PIC 12F GPIO
>> pin, is the fact
>>  that the TRISIO register is set for input at power up
>> sufficient to stop
>>  random triggering  or should I be looking at some kind
>> of
>>  buffer/interlock between the PIC IO pin and the MOSFET?

> Normallly, you'd use resistors to pull those lines to a
> defined state
> while the uP is in reset or getting initialized.
> Otherwise, who knows
> what happens?

Murphy does.
And others can guess reasonably well :-).

*IF* the pin can be guaranteed to be high impedance or
driven low at ALL stages of processor power up and power
down then a pull down resistor should suffice.

Even then:
If it is utterly vital that the gate never glitch high then
a hardware interlock is utterly vital.
If it is vaguely important that the gate never glitch high
then a hardware interlock is from vaguely important to not
important at all.

ie you should be able to obtain a defined startup condition
if the processor guarantees the pin state is known under all
circumstances. But even then, if lives depend on it, then
you shouldn't.



       Russell

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