Post by thread:PC Port Help

I need a quick hand, and I don't have my tools handy. Can you help? I need to kick-start the UART in a PC to make it start talking. The whole app is interrupt-driven, so either I need a way to force a call to my ISR with the appropriate flag bits set in the UART status register, or some other idea. How about URL? I'm off yahoo already. Thanks. Andy ================================================================== Andy Kunz Life is what we do to prepare for Eternity ------------------------------------------------------------------ spam_OUTandyTakeThisOuTrc-hydros.com http://www.rc-hydros.com - Race Boats .....andyKILLspam@spam@montanadesign.com http://www.montanadesign.com - Electronics ==================================================================

>From http://www.senet.com.au/~cpeacock/serial.htm#15 01h 3F9h Interrupt enable register Setting the mode of interrupt request Bit Notes Bit 7 Reserved Bit 6 Reserved Bit 5 Enables Low Power Mode (16750) Bit 4 Enables Sleep Mode (16750) Bit 3 Enable Modem Status Interrupt Bit 2 Enable Receiver Line Status Interrupt Bit 1 Enable Transmitter Holding Register Empty Interrupt Bit 0 Enable Received Data Available Interrupt The Interrupt Enable Register could possibly be one of the easiest registers on a UART to understand. Setting Bit 0 high enables the Received Data Available Interrupt which generates an interrupt when the receiving register/FIFO contains data to be read by the CPU. Bit 1 enables Transmit Holding Register Empty Interrupt. This interrupts the CPU when the transmitter buffer is empty. Bit 2 enables the receiver line status interrupt. The UART will interrupt when the receiver line status changes. Likewise for bit 3 which enables the modem status interrupt. Bits 4 to 7 are the easy ones. They are simply reserved. (If only everything was that easy!) 02h 3FAh Interrupt identification register Checking the mode of interrupt request Bit Notes Bits 6 and 7 6 7 0 0 No FIFO 0 1 FIFO Enabled but Unusable 1 1 FIFO Enabled Bit 5 64 Byte Fifo Enabled (16750 only) Bit 4 Reserved Bit 3 0 Reserved on 8250, 16450 1 16550 Time-out Interrupt Pending Bits 1 and 2 2 1 0 0 Modem Status Interrupt 0 1 Transmitter Holding Register Empty Interrupt 1 0 Received Data Available Interrupt 1 1 Receiver Line Status Interrupt Bit 0 0 Interrupt Pending 1 No Interrupt Pending The interrupt identification register is a read only register. Bits 6 and 7 give status on the FIFO Buffer. When both bits are '0' no FIFO buffers are active. This should be the only result you will get from a 8250 or 16450. If bit 7 is active but bit 6 is not active then the UART has it's buffers enabled but are unusable. This occurs on the 16550 UART where a bug in the FIFO buffer made the FIFO's unusable. If both bits are '1' then the FIFO buffers are enabled and fully operational. Bits 4 and 5 are reserved. Bit 3 shows the status of the time-out interrupt on a 16550 or higher. Lets jump to Bit 0 which shows whether an interrupt has occurred. If an interrupt has occurred it's status will shown by bits 1 and 2. These interrupts work on a priority status. The Line Status Interrupt has the highest Priority, followed by the Data Available Interrupt, then the Transmit Register Empty Interrupt and then the Modem Status Interrupt which has the lowest priority. James Newton, webmaster http://get.to/techref jamesnewtonKILLspamgeocities.com <.....jamesnewtonKILLspam.....geocities.com> 1-619-652-0593 phoneÊ {Original Message removed}

Thanks to all for the help. The best helps I found were http://www.lammertbies.nl and ftp://ftp.psyber.com/tcj/faqs/asyam.zip (the latter is some truly NICE and POWERFUL code) Andy ================================================================== Andy Kunz Life is what we do to prepare for Eternity ------------------------------------------------------------------ EraseMEandyspam_OUTTakeThisOuTrc-hydros.com http://www.rc-hydros.com - Race Boats andyspam_OUTmontanadesign.com http://www.montanadesign.com - Electronics ==================================================================