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'New PIC technology wish list.'
1997\08\10@104055 by Kalle Pihlajasaari

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Hi Dreamers,

Here is a few Ideas I have had that would allow MicroChip to forge
ahead in the uChip field.  Nothing new, just not seen them mentioned
here before.

These are all ideas for getting more speed or better interrupt response.


1 . Reduce the clock phases to one per instruction cycle.  :-)

2 . Increase all silicon speed to 35 MHz.

3 . Widen stack to accommodate the W register

4 . Widen stack to accomodate STATUS register.

5 . Prefetch instruction at the interrupt vector
   so there is no prefetch required on an interrupt context
   switch going in.

6 . Widen stack to store instruction that was prefetched
   and usually discarded so return places correct instruction
   in pipeline.  This would also mean regular returns would
   be single cycle instruction as they would have the next
   instruction already available.

7 . Double the stack depth to 16 to allow compilers more freedom.

The fists 6 points above would reduce the interrupt latency from
9 cycles at 5 Mips to 2 cycles at 35 Mips.

An incease of Interrupt response of 31.5 TIMES for very minimal
changes to the core and no foundermental code compatibility
issues, could add a bit to turn on fast interrupt mode if required.

Obviously pin drive and such would get to be more of a problem at
35 Mips but FPGAs can do this and even the new Parallax SX Key looks
like it can do it (they just use 200 MHz silicon I think though).

Any comments, those from Microchip always welcome :->

Cheers
--
Kalle Pihlajasaari   spam_OUTkalleTakeThisOuTspamip.co.za   http://www.ip.co.za/ip
Interface Products   P O Box 15775, DOORNFONTEIN, 2028, South Africa
+ 27 (11) 402-7750   Fax: 402-7751    http://www.ip.co.za/people/kalle

DonTronics, Silicon Studio and Wirz Electronics uP Product Dealer

1997\08\10@122159 by Mike Keitz

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On Sun, 10 Aug 1997 15:53:05 +0200 Kalle Pihlajasaari
<.....kalleKILLspamspam@spam@DEVICE.DATA.CO.ZA> writes:
>Hi Dreamers,
>
>Here is a few Ideas I have had that would allow MicroChip to forge
>ahead in the uChip field.  Nothing new, just not seen them mentioned
>here before.

You haven't been watching very closely then.  In particular, ideas about
stacking W and STATUS have been discussed to death recently.

>These are all ideas for getting more speed or better interrupt
>response.

One of the nice things about the PIC interrupt response compared to many
other processors is that it's constant.  No matter what the program is
doing, the time from the interrupting event to execution of the first
instruction in the ISR is always the same.  This makes a lot of tricks
possible.  I would not want "enhancements" that take this away.

>1 . Reduce the clock phases to one per instruction cycle.  :-)

Someone mentioned one of the "Future products" could contain a PLL clock
multiplier to make the internal clock 4x the crystal clock, thus one
instruction per crystal cycle.  This is going to be necessary to increase
the top speed of the PIC, since making crystals work much higher than 30
MHz is difficult.  But the multiplier will likely increase the cost,
increase the power consumption, and limit the minimum speed.  Changing
the core itself to run 1 instr per cycle is likely not feasible and it
would certainly introduce a lot of multiple cycle instructions and other
special cases that would complicate programming.


>
>2 . Increase all silicon speed to 35 MHz.

Most of us usually use 4MHz or below and would not want to pay for 35 MHz
silicon.  Slow silicon can likely be made in a dirty old factory compared
to an expensive new one and thus has the potential to lower the price.

[...]
>Obviously pin drive and such would get to be more of a problem at
>35 Mips but FPGAs can do this and even the new Parallax SX Key looks
>like it can do it (they just use 200 MHz silicon I think though).

Slow IO pins are no problem other than tring to RMW output ports, which I
consider to be bad practice anyway.  I like the PIC's ability to sink
*and source* 20 mA per pin.

Things I'd like to see (in no particular order)

- Lower the price.

- More RAM.  More RAM.  A couple of applications I'm thinking of would
need abut 2K of RAM.  This isn't going to happen on any of the PICs (or
AVRs for that matter) even the so-called "high-end" ones. Interface logic
(such as address/data multiplexers) could be added to the ports for easy
and moderately high-performance (ideally using sub instr cycle
resolution) connection of external RAM, either SRAM or DRAM.

- Really shake up the memory map.  Right now little chunks of RAM are
here and there, and it is all paged so global data is hard to get to.
Change the RAM banking so the first 128 locations are unbanked and a bank
select register selects pages for the upper 128.  (Put *all* SFRs in the
first 128 so they can be accessed directly at any time and fill the rest
with RAM).  Access to large data structures would be much simplified by
just slipping one bit out of FSR and into the bank register.  And the
data that isn't part of the large structure would stay put.

- Hardware UARTs, capture timers, etc. on an 18-pin or smaller chip.

- A chip with internal EEPROM and more than 1K of program memory.
Hopefully this can be done in the short term.

1997\08\10@135518 by John Payson

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> - More RAM.  More RAM.  A couple of applications I'm thinking of would
> need abut 2K of RAM.  This isn't going to happen on any of the PICs (or
> AVRs for that matter) even the so-called "high-end" ones. Interface logic
> (such as address/data multiplexers) could be added to the ports for easy
> and moderately high-performance (ideally using sub instr cycle
> resolution) connection of external RAM, either SRAM or DRAM.
>
> - Really shake up the memory map.  Right now little chunks of RAM are
> here and there, and it is all paged so global data is hard to get to.
> Change the RAM banking so the first 128 locations are unbanked and a bank
> select register selects pages for the upper 128.  (Put *all* SFRs in the
> first 128 so they can be accessed directly at any time and fill the rest
> with RAM).  Access to large data structures would be much simplified by
> just slipping one bit out of FSR and into the bank register.  And the
> data that isn't part of the large structure would stay put.

Look at Microchip's future products guide.  While I'm not sure how they plan
to have 128K of linerarly-addressible code space on a part with a 16-bit
instruction word, they do claim a 4K linear data address space.

> - A chip with internal EEPROM and more than 1K of program memory.
> Hopefully this can be done in the short term.

Also listed in the future products guide.

1997\08\11@103418 by Martin R. Green

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Mike Keitz said:

>Things I'd like to see (in no particular order)

...snip

>- Hardware UARTs, capture timers, etc. on an 18-pin or smaller chip.

Here, here (hear, hear?)!  And full I2C slave and master controllers on the
small chips too (although the way the bigger chips work, this would
probably be true if the chip had a hardware UART).

Martin R. Green
elimarspamKILLspambigfoot.com

1997\08\11@145514 by Andy Kunz

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One thing that's driving me nuts on several projects is that there isn't a
windowed surface mount version.  I'm getting around it when in the emulator
by using a SMT-to-DIP adapter (from Digi-Key parts from AMP plus a custom
PCB), but sometimes there just ain't enough room in the target.

So how about, MCHP?  Make us /JWSM chips!  (I don't care if they cost
$50.00 each, JUST MAKE 'EM!)

Andy

==================================================================
Andy Kunz - Montana Design - 409 S 6th St - Phillipsburg, NJ 08865
         Hardware & Software for Industry & R/C Hobbies
       "Go fast, turn right, and keep the wet side down!"
==================================================================

1997\08\12@013551 by tjaart

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Andy Kunz wrote:
>
> One thing that's driving me nuts on several projects is that there isn't a
> windowed surface mount version.  I'm getting around it when in the emulator
> by using a SMT-to-DIP adapter (from Digi-Key parts from AMP plus a custom
> PCB), but sometimes there just ain't enough room in the target.
>
> So how about, MCHP?  Make us /JWSM chips!  (I don't care if they cost
> $50.00 each, JUST MAKE 'EM!)

Hi Andy (#?)

They actually do - the 16C924 CL (Windowed CERQUAD)

We slapped a lot of defective '74 QFP's onto PC boards some time ago.
It would have been cheaper for us to use $50 windowed versions and
being able to work around the problem, than reworking SMD boards.

We were promised replacements, but are still waiting...

--
Friendly Regards

Tjaart van der Walt
.....tjaartKILLspamspam.....wasp.co.za
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1997\08\12@062617 by Steve Lawther

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    Andy,
   
    I've heard a rumour that your wish may be coming true in the next
    month or two. - even on the 12Cxxx series! (no guarantees thou, as
    it's a second hand rumour - I didn't get it from the microchip guy
    myself)
   
   
               Steve


______________________________ Reply Separator _________________________________
Subject:      Re: New PIC technology wish list.
Author:  MIME:EraseMEmontanaspam_OUTspamTakeThisOuTFAST.NET at INTERNET-HUSKY
Date:    11/08/97 20:15


One thing that's driving me nuts on several projects is that there isn't a
windowed surface mount version.  I'm getting around it when in the emulator
by using a SMT-to-DIP adapter (from Digi-Key parts from AMP plus a custom
PCB), but sometimes there just ain't enough room in the target.
   
So how about, MCHP?  Make us /JWSM chips!  (I don't care if they cost
$50.00 each, JUST MAKE 'EM!)
   
Andy
   
==================================================================
Andy Kunz - Montana Design - 409 S 6th St - Phillipsburg, NJ 08865
         Hardware & Software for Industry & R/C Hobbies
       "Go fast, turn right, and keep the wet side down!"
==================================================================
   

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