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'Multiple PIC's, one OSC.'
1999\10\13@212314 by Thomas Brandon

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Is it possible to run multiple PIC's of one oscillator source. I don't want
them synced or anything (I know the Q cycles will be out), it's a board
space and (possibly) a calibration issue. Have a project that will prob.
require multiple PIC's. Be much nicer to have 1 oscillator. Ideally it
wouldn't matter how many PIC's were hooked up (but this may not be possible
with reasonable accuracy due to load). The other advantage of this is a
single clock calibration routine. If calibration was an issue then all chips
should be able to be calibrated simultaneously (assuming the design kept the
clock equal at all PICs), thus if the calibration were off slightly it
should be off for all PICs and there shouldn't be drift between PICs
(although I don't need to count on this and wouldn't unless absolutely
neccesary).

I must say, a Q cycle synchronisation capability would be a fantastic
addition for multi PIC projects. Something like the synchronisation scheme
used in multimaster I2C (from memory) to obtain clock sync. The basic idea
of this would be a Clock hold pin on your PIC's. If this pin were held low
the PIC would not be able to rollover from Q4 to Q1, hence you would tie
this pin of your PIC's together, hold it low for a few cycles (after OSC
startup) to get all the PIC's at the Q4->Q1 transition, then let it go high,
this would cause all PIC's to start at Q1 at the same time. Of course this
relies on all PIC's having identical clocks (have to be careful of rise\fall
times due to capacitances etc), and prob. wouldn't be exactly rock solid.
But If you could hold them steady for a few million cycles between resync's
it would allow extremely fast (theoretically at the clock rate) data
transfers with no physical synchronisation. Ideally you could set up the
hardware to, do automatic synching (e.g. every X million cycles, do a 4
cycle sync). Don;t know if it'd work in practice but I like it in theory.

Tom.

1999\10\13@222250 by Sean H. Breheny

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Yes,it is possible. The best way is to use an external oscillator with
sufficient drive and then route the output to all of the OSCIN pins on the
PICs (I forget which pin this is,but it's in the datasheet). I think you
also want to put the PIC in HS mode (again, going from memory, it might be
XT).

A thought occured to me about the synchronization: Commands like BSF and
BCF should always output to the port pins on the same cycle,right(I think
its Q4)? Why not make a piece of hardware which sends the clock to several
PICs simultaneously. However, to sync them, it runs the clock very slow and
withholds the clock from all but one PIC at a time. Each PIC is programmed
with several BSF and BCF commands. The clock hardware would feed the clock
to each PIC individually until it saw a rising edge (BSF) on an output pin.
It would then go to the next PIC, do the same. Then, you would have all the
PICs at the same Q phase,and you could simultaneously feed the normal fast
clock,and the special clock gen could be turned off. The special clock
circuit could even be a PIC itself.

Can anyone see any problems with it?

Sean

At 11:26 AM 10/14/99 +1000, you wrote:
{Quote hidden}

| Sean Breheny
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| Electrical Engineering Student
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1999\10\13@222755 by Richard Prosser

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This came up a week or so ago & got me thinking.

1.      You should be able to feed 2 (or more) PICs from an external osc. or
even feeding the input side  of the second from the xtal drive (output) side
of the other. Possibly at the highest frequencies it may be dubious but in
the middle range I don't see why not.

2.      Q Cycle synchronising. With the PICs that have PWM output the Q
cycle is available (e.g. the '73s will produce a 10 bit resolution with the
LSB corresponding to a single oscillator cycle). Therefore, it should be
possible to use a PLL to synchronise the two clocks & processors down to
this level. You may need additional synchronisation to achieve an
approximate setting first but after that the Q cycle PLL could take over. As
you say, rise and fall times may need looking at carefully for actual
communication (along with port read/write timing) but it could be worth
looking at, particularly if in the case of parallel processing.

Anyone else any ideas on this?

Richard P


> {Original Message removed}

1999\10\14@124755 by Harold M Hallikainen

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On Wed, 13 Oct 1999 22:19:31 -0400 "Sean H. Breheny" <.....shb7KILLspamspam@spam@CORNELL.EDU>
writes:
{Quote hidden}

       This reminds me of the old weather map fax machines I used to
work on for the FAA.  They used soggy paper and passed current thru the
paper to turn a pixel brown.  The paper was pulled over a drum that
rotated with a helix contact on it.  There was also a contact band above
the paper.  As the drum rotated, we got a horizontal scan across the
page.  The motion of the paper gave the vertical scan.  At the beginning
of each map was a black bar with a white horizontal sync pulse.  On
detecting this, the oscillator that drove the synchronous motor driving
the helix drum changed from 60 Hz to 59 Hz or so.  The motor would
continue to run at this speed until a magnetic reed switch on the side of
the drum closed during the received sync pulse, indicating the sync pulse
was now at the edge of the picture.  The motor then changed back to 60
Hz.  At the top of each map was this black bar with a white diagonal
stripe going down and to the left until it hit the left end of the paper.
       The oscillator for the motor was a crystal oscillator with a
digital divider chain.  As I recall, they changed the digitial division
ratio to slow the motor down.  The oscillator/divider chain then drove a
big transistorized power amp that drove the motor.  The only problems we
EVER had with the machine were due to the power amp blowing up.

Harold



Harold Hallikainen
haroldspamKILLspamhallikainen.com
Hallikainen & Friends, Inc.
See the FCC Rules at http://hallikainen.com/FccRules and comments filed
in LPFM proceeding at http://hallikainen.com/lpfm

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