Post by thread:Logic substitutes

Hi all Ive got a circuit design that uses 4 or 5 TTL chips to take in 16 address lines to enable various peripherals. Im looking to reduce the IC count to 1 chip. Ive heard about pal,gal and pld chips but have no idea how to use them or program them. Would these chips suit the job and if so where do I learn about them? Also, would a pic chip be fast enough to substitute a logic device? Thanks Justin

ALTERA has some free software development on their website for doing EPLD designs, but if I recall, it does not support the JTAG or ISP functions (too bad). Something like a 7032 (32 macrocells) might work pretty nice. There was someone that had info here on LATTICE as well, but they were bought by....someone else now? Not sure what the latest story is on that since I don't use any of these parts. But they were one of the first to support ISP. XILINX has had a range of EPLD's, and just finished buying Phillips COOLRunner line (low power parts). And they may also have free development software as well, using ISP. They have a couple smaller parts, like 32 and 128 macrocell devices. I don't keep up to date on free development since we are large user of these parts and basically get the software free or very cheap (they finally realize that without software, we don't use the silicon). You could use a PIC of course, just make sure that its running at a faster clock than what your system is running else you end up having problems in race conditions.

On Wed, Aug 04, 1999 at 07:17:50PM +0800, Justin Grimm wrote: > Hi all > Ive got a circuit design that uses 4 or 5 TTL chips to take in > 16 address lines to enable various peripherals. > Im looking to reduce the IC count to 1 chip. > Ive heard about pal,gal and pld chips but have no idea how > to use them or program them. Would these chips suit the job > and if so where do I learn about them? The manufacturers would be a good start. Lattice/Vantis, Xylinx, Atmel, Cypress, etc. Several offer free or eval design software. Atmel even offers a free CD (ISD 6.0) that includes a license for the Everest synthesis software. Also, a good portal site for programable logic is the "Programmable Logic Jump Station" at http://www.optimagic.com Generally, in programmable logic, there originally were PLDs, PALs, GALs, etc -- those tend to be quite simple and limited in function. The next step up are the CPLDs, (Complex PLDs) which in essence amount to a whole bunch of PLDs with an interconnect fabric. The high end devices are FPGAs, which is undoubtedly way overkill to replace a few TTL chips; among other things, the FGPAs have huge pin counts, and often need external EPROM or flash ROM to boot from. If you're using a uC with a real memory bus, Waferscale (http://www.waferscale.com) has an interesting device that integrates Flash memory, SRAM and a 16-cell CPLD on the same chip. > Also, would a pic chip be fast enough to substitute a logic > device? > Thanks > Justin I would imagine that the main concern would be latancy, and possibly pin count. There is actually a Microchip Ap Note (511, at www.microchip.com/10/Appnote/Category/16C5X/00511/index.htm software at http://www.microchip.com/10/Appnote/Category/16C5X/00511/idxZIP0.htm) on using a PIC16C5x as a replacement for a PLD. --Bob -- ============================================================ Bob Drzyzgula It's not a problem spam_OUTbobTakeThisOuTdrzyzgula.org until something bad happens ============================================================

> > On Wed, Aug 04, 1999 at 07:17:50PM +0800, Justin Grimm wrote: > > Hi all > > Ive got a circuit design that uses 4 or 5 TTL chips to take in > > 16 address lines to enable various peripherals. > > Im looking to reduce the IC count to 1 chip. > > Ive heard about pal,gal and pld chips but have no idea how > > to use them or program them. Would these chips suit the job > > and if so where do I learn about them? I'd use a Scenix SX18 chip. Quick, dirty, cheap. -- Friendly Regards /"\ \ / Tjaart van der Walt X ASCII RIBBON CAMPAIGN .....tjaartKILLspam@spam@cellpt.co.za / \ AGAINST HTML MAIL |--------------------------------------------------| | GSM Technology for Positioning and Telematics | | Cellpoint Systems SA http://www.cellpt.com | | http://www.wasp.co.za/~tjaart/index.html | | WGS84 -26.0124 +28.1129 Voice +27 (0)11 2545100 | |--------------------------------------------------|

RAM based ispGALs are called Field Programmable Gate Arrays (FPGAs). They must be reprogrammed each time on power up (which requires time and introduces a delay that may be unacceptable in some applications) but can be reprogrammed as often as desired. FLASH based ispGALs are called Complex Programmable Logic Devices (CPLDs). Hold their programming in non-volatile FLASH or EEPROM memory and so fire up ready to go. Unfortunately, FLASH or EEPROM memory does have a limited life so CPLDs can not be reprogrammed continuously. Software to translate HDL description of circuits into JDEC files, program the JDEC files into the individual devices and the interconnection cable between the PC and the device via an adapter socket or ISP header costs thousands of dollars. You can get started for quite a bit less. Xilinx sells a student edition for about $99. It is crippled in that it is limited in the size device it can compile. Still, the devices it handles are plenty big to do many things, especially learn about the device capabilities. That package has a schematic entry capture tool. While the industry is pushing hard toward text based entry, lack of knowledge of the device architecture will not let you exploit the device to anywhere near its potential. I highly recommend newbies start out with schematic entry and use it until they at least become comfortable with the device structure and tools and what works and doesn't work. Once you have that down, then you are welcome to fight with the VHDL tools to make them do what you've learned is the best implementation for what you want to do. One of the weaknesses of the foundation schematic capture is its poor handling of hierarchy. In viewlogic, you can easily encapsulate a design as a macro to be used in a larger design. XILINX says it will improve this with version 2.1i expected in fall MANUFACTURERS: Actel http://www.actel.com FLASH based (but they refer to their "AntiFuse" technology line as FPGAs). The Actel DeskTOP software CD is free (with registration) until January 31, 2000 But the programmers are high cost. Lattice/Vantis http://www.lattice.com Flash based. You can download free programming software and burn the chips in system with a cable they would like to sell you. The Lattice Semiconductor ispGAL22V10 was the first isp pin-for-pin replacement for the popular GAL22V10 chip (12 inputs and 10 outputs, 8 to 12 terms per output) . A PC parallel port programming cable design with free programming software for use with palASM was presented in Circuit Cellar Ink #65 December 1995 "In-Circuit-Programmable GALs" The inexpensive ispLSI 1016 gives you about 90 flipflops Ê64 terms and 36 io pins and works fine with tact rates above 50 Mhz. Lattice acquired Vantis http://www.vantis.com, makers of the MACH series CPLDs, PALÊispGALs and Design Direct software. The base version of the software is free (6 months) and a very general schematic for the programming cable is available. They have an app-note on "JTAG In-System Configuration with an Embedded Processor". They claim to be working on a line of FPGAs. Xilinx http://www.xilinx.com RAM and FLASH based. The XP3020 is available from DigiKey Corp (comparison matrix) with 64 io pins for about $13.50 qty 1 to $11 each in gross quantities. It is RAM based and can be programmed from an embedded controller on power up via 3 pins. The protocol is well documented but no sample code appears to be available. The least expensive software support appears to be the $99 student edition of the Foundation software. Xess Corp http://www.xess.com/fpga provides solutions Altera http://www.altera.com FLASH based. The schematic is available for the "ByteBlaster" PC parallel port programmingÊcable (a 74HC244 and some resistors) can be used to program most Altera devices. The JAM ISP programming language player development kit with C source code is available (must agree to license) and can be implemented in an embedded processor to program embedded devices. A PC parallel port programming cable (no buffer chip) and programming software was presented in Circuit Cellar Ink #65 December 1995 article "Low Cost FPGA Development System" by ?? of Xess Corp used the Altera EPX780 CPLD which was available from JDR Microdevices and DigiKey Corp but was replaced by a flash based EPX880 which was then discontinued. Cypress Programmable Logic http://www.cypress.com/pld/index.html EPROM and FLASH based. Inexpensive ($99) software and ($179) kit with ISP cable. See also: Circuit Cellar Ink #65 December 1995 "In-Circuit-Programmable GALs" and "Low-Cost FPGA Programmer" XESS Corp FPGA examples and solutions Oki Semiconductor "Vhdl for Programmable Logic" Addison-Wesley Pub Co; ISBN: 0201895730 from Amazon.com $53.95 http://www.iowegian.com/loadfir.htm - programming FPGA's from VDHL descriptions. http://www.wmdsp.com/ Linux http://www.optimagic.com/index.shtml lots of information and products: http://www.fliptronics.com/flibgen.html Module generator for Xilinx XC4000E, XC4000XL, XC4000XLA, SPARTAN, and SPARTANXL http://users.ids.net/~randraka/ lots of good tech data in-between the sales hype. Logic that mutates while-u-wait by Clive "Max" Maxfield, Intergraph Computer Systems James Newton, webmaster http://get.to/techref jamesnewtonKILLspamgeocities.com <.....jamesnewtonKILLspam.....geocities.com> 1-619-652-0593 phoneÊ {Original Message removed}

> > > > On Wed, Aug 04, 1999 at 07:17:50PM +0800, Justin Grimm wrote: > > > Hi all > > > Ive got a circuit design that uses 4 or 5 TTL chips to take in > > > 16 address lines to enable various peripherals. > > > Im looking to reduce the IC count to 1 chip. > > > Ive heard about pal,gal and pld chips but have no idea how > > > to use them or program them. Would these chips suit the job > > > and if so where do I learn about them? > > I'd use a Scenix SX18 chip. Quick, dirty, cheap. > > -- > Friendly Regards /"\ > \ / > Tjaart van der Walt X ASCII RIBBON CAMPAIGN > I'd say it depends totaly on the speed of your circuit. If this is the address bus of a microcontroler/microprocessor(and it sounds like it), then even a 50Mhz Scenix may give an unnaceptable latency. With 16 address lines to read and process, I would think that you would be looking at a latency in the microsecond region which is way too slow unless your micro is running at much less than 1Mhz. Certainly it won't come close to the speed of a GAL, which is in the 10's of nanoseconds range. Just my 2 cents, I haven't used the Scenix so it may be much more capable than I think. Cheers Mike Rigby-Jones

This is interesting. I thought that we were actually getting away from text based tools in favor of graphical development tools. What is the rationale? Martin McCormick James Newton writes: >That package has a schematic entry capture tool. While the industry is >pushing hard toward text based entry, lack of knowledge of the device >architecture will not let you exploit the device to anywhere near its >potential. I highly recommend newbies start out with schematic entry and = >use >it until they at least become comfortable with the device structure and >tools and what works and doesn't work.

HDL, be it verilog, vhdl or AHDL or whatever, lends itself to be more portable, and can also be applied to various synthesis tools. Also, because it is text based, it does not depend on the tool being able to read in the file from an earlier version. I've been bit by that before as well. Its also easier to define registers and such. Especially wide registers, rather than draw and label a bunch of busses and try and connect them together. -----Original Message----- From: Martin McCormick [EraseMEmartinspam_OUTTakeThisOuTDC.CIS.OKSTATE.EDU] Sent: Wednesday, August 04, 1999 12:06 PM To: PICLISTspam_OUTMITVMA.MIT.EDU Subject: Re: Logic substitutes This is interesting. I thought that we were actually getting away from text based tools in favor of graphical development tools. What is the rationale?

Well, there seems to be a shift to language based entry as the complexity of the design increases. Most of the complex IPs I have browsed have looked more like programs than schematics. For example, its much easier to understand a design that implements a state machine when viewed as a table than as the mess of logic gates that implement it. I may be wrong, but it seems like iconic systems break down quickly as complexity increases, where as language simply encapsulates complex new concepts with a single new word. In schematic systems only a few devices have a different symbol. ICs of medium complexity and higher are all represented basically as boxes. The text inside the box identifies the function. Flow charts show the same limitations. But those of us who are brain damaged and not able to easily wrap our minds around HDL syntax find schematic capture much easier to start with for our simple projects. Its great to be able to look at a schematic and then see the text generated for that schematic as a way to learn the HDL. James Newton, webmaster http://get.to/techref @spam@jamesnewtonKILLspamgeocities.com <KILLspamjamesnewtonKILLspamgeocities.com> 1-619-652-0593 phone {Original Message removed}

If it's a fairly slow device a EPROM programmed with a table might do as a 12 (or more) to 8 (or more) enables I have used this in sub 1mhz devices with success peter > {Original Message removed}

Michael Rigby-Jones wrote: > > > > > Hi all > > > > Ive got a circuit design that uses 4 or 5 TTL chips to take in > > > > 16 address lines to enable various peripherals. > > > > Im looking to reduce the IC count to 1 chip. > > > > Ive heard about pal,gal and pld chips but have no idea how > > > > to use them or program them. Would these chips suit the job > > > > and if so where do I learn about them? > > > > I'd use a Scenix SX18 chip. Quick, dirty, cheap. > > > I'd say it depends totaly on the speed of your circuit. If this is the > address bus of a microcontroler/microprocessor(and it sounds like it), then > even a 50Mhz Scenix may give an unnaceptable latency. With 16 address lines > to read and process, I would think that you would be looking at a latency in > the microsecond region which is way too slow unless your micro is running at > much less than 1Mhz. Certainly it won't come close to the speed of a GAL, > which is in the 10's of nanoseconds range. If you want more address lines, you can use a SX28. Each instruction takes about 20ns, and you are in control of what comes out the ports, so you could have a glitch-less glue chip. I'd say a few hundreds of ns would do it. I agree about the speed of the GAL - it is real fast. It is just a pain in the butt (IMHO) to implement and develop on for a beginner. -- Friendly Regards /"\ \ / Tjaart van der Walt X ASCII RIBBON CAMPAIGN RemoveMEtjaartTakeThisOuTcellpt.co.za / \ AGAINST HTML MAIL |--------------------------------------------------| | GSM Technology for Positioning and Telematics | | Cellpoint Systems SA http://www.cellpt.com | | http://www.wasp.co.za/~tjaart/index.html | | WGS84 -26.0124 +28.1129 Voice +27 (0)11 2545100 | |--------------------------------------------------|

I am curious as to what the code of a logic array program looks like. Is there a site of any kind on the Internet that I can go to which has samples? If I can learn how to use this technology, it along with PIC's should turn most projects in to a much smaller package. Martin McCormick

You can't beat the articles in the Circuit Cellar Ink #65 December 1995 issue for an introduction and samples: "Low Cost FPGA Development System" see also http://www.xess.com/FPGA and "In-Circuit-Programmable GALs". Back issue is available electronically at http://www.circuitcellar.com/cds_available.htm The following sites list Free(?) Intellectual Properties (applications for FGPAs or CPLDs) www.scsise.wmin.ac.uk/~seamang/freehardware.html http://www.cmosexod.com/ http://circu.its.tudelft.nl/ www.scsise.wmin.ac.uk/~seamang/freehardware.html http://www.scrap.de/html/openip.htm www.geocities.com/SiliconValley/Chip/5014/ http://www.vhdl.org/vi/fmf/ tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html dmoz.org/Computers/Open_Source/Hardware/ http://www.mindspring.com/~tcoonan freeware Verilog PIC CPU core http://www.silicore.net. Pro PIC CPU core. http://www.fpga-design.com/ James Newton, webmaster http://get.to/techref spamBeGonejamesnewtonspamBeGonegeocities.com <TakeThisOuTjamesnewtonEraseMEspam_OUTgeocities.com> 1-619-652-0593 phoneÊ {Original Message removed}

Check out the Altera site; their "baseline" EPLD compiler is downloadable for free. I've done several designs with the Altera "MAX+plusII" compiler and found it very easy: you may describe your design in sort of a high-level language, or use standard schematic building blocks, whatever you like better. Using a "sea of gates" like Altera FLEX that is configured after power-up by downloading of a config stream from special EEPROM or a microcontroller is a terrific way to create extremely flexible solutions fast, but I think this may be oversized for a PIC. Maybe the EPLD types like MAX7000 may be more suitable. If you want an example source, email me at: RemoveMErkoehler_ddTakeThisOuTcsi.com Roland Koehler.

Justin, depending on speed, you might want to consider a CPLD. I have a lot of experience with Lattice Semiconductor. The Lattice ispLSI1016E-100LJ is a 100MHz 44-pin PLCC device. It costs around $6-$7 in single quantity. It's hard to explain the device's resources without having studied the architecture. It includes: 32 I/Os 4 Dedicated Inputs 3 Clock Inputs 1 Global Reset shared with one of the clock Inputs 1 Global Output-Enable shared with one of the Dedicated Inputs 2000 Gates 96 Registers 16 Generic Logic Blocks (GLB) Again, there is more to it. Those resources are arranged in GLBs or Generic Logic Blocks. They include several options such as hardware XOR gates, OR gates, product term Resets, Output-Enables, and Clocks. Each GLB includes 4 registers which can be configured in several ways. There is also a `High Speed Bypass" option to route product term outputs directly to the output macrocells. Output macrocells can be configured in a variety of ways such as Inputs, Outputs, Latched Input, Bi-Directional with or without Latched Inputs, and 3-State. Lattice currently provides the ispExpert software with a free six month license. This is an update to the Synario package which Lattice acquired. It provides schematic and ABEL-HDL entry. Also included is a gate-level functional and timing simulator. There is a lot more to the package but it's very easy to use. It supports most of their devices as well as generic GALs. Programming is trivial with just a 5V supply. The Lattice software to do this is free. The download cable uses a 74HC/LS367 and a few passives and connects to a PC parallel port. Most folks already have the parts in their `stash'. To build the Lattice download cable, see my web page at: http://www.teleport.com/~thandley/Wilbure.htm For more information about Lattice Semiconductor's products and to download the ispExpert design software, contact: http://www.latticesemi.com - Tom On Wed, Aug 04, 1999 at 07:17:50PM +0800, Justin Grimm wrote: > Hi all > Ive got a circuit design that uses 4 or 5 TTL chips to take in > 16 address lines to enable various peripherals. > Im looking to reduce the IC count to 1 chip. > Ive heard about pal,gal and pld chips but have no idea how > to use them or program them. Would these chips suit the job > and if so where do I learn about them? ------------------------------------------------------------------------ Tom Handley New Age Communications Since '75 before "New Age" and no one around here is waiting for UFOs ;-)