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PICList Thread
'LVP of 16f877 (RB3/PGM)'
1999\10\23@140444 by Jason Muhammad

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I do not know why Microchip would stick the Programming pin (RB3) in the
middle of a port (RB0-RB7)...  Why not Bit7 of a port so you would
read/write 0x00-0x7F?

Anyway, if RB3 ceases to be a GenPurpose I/O, when you read the port,
what does the Bit3 read as (0 or 1)?
Is the lower nibble Octal and the upper nibble Hex?

If I use LPV, I am going to redefine RB4-RB7 as RB3-RB6 so I can
read/write 0x00-0x7F.  I will NOT call RB3/PGM this, I will refer it as
PGM only.  Hence, PortB will become a 7pin port.  Less confusing.  What
do you think?

--
Jason
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1999\10\23@175903 by paulb

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Jason Muhammad wrote:

> I do not know why Microchip would stick the Programming pin (RB3) in
> the middle of a port (RB0-RB7)...  Why not Bit7 of a port so you would
> read/write 0x00-0x7F?
...
> Less confusing.  What do you think?

 I think it's a right foul-up!  As I see it, LVP is basically un-usable
and you need to use a 12V programmer and *always* disable it.

 Otrherwise regard PortB as a second PortA - incomplete, unsuitable for
parallel byte-wise transfer.

 It appears to be a truly amazing extension of their design psychosis;
like saying you shouldn't use OPTION and TRIS instructions which *are*
still perfectly valid on this processor but won't work on the only truly
byte-wide port remaining, where you probably most *NEED* to use TRIS!

 (Or will it?)
--
 Cheers,
       Paul B.

1999\10\24@063041 by Robin Abbott

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Yes, this amazed (and really annoyed me as a programmer designer and PIC
program author). Scenix use the oscillator pins, surely Microchip could have
come up with something using the OSC pins, MCLR and the existing programming
pins ?

Robin Abbott - .....robin.abbottKILLspamspam@spam@fored.co.uk

**************************************************************************
*
* Forest Electronic Developments
* http://dspace.dial.pipex.com/robin.abbott/FED
*
**************************************************************************

{Original Message removed}

1999\10\24@080825 by Tom Handley

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  Paul (and Jason), without knowing the details of the process and the
`floor plan' of the chip, I can only speculate. RB4..7 have additional logic
for the interrupt-on-change feature as well as RB0 for external interrupts.
RA has analog and timer inputs. RC has many functions and RD and RE are
normally used for a standard parallel bus interface. I really wish they
would have used RA5 but they would probably have to sacrifice an A/D channel
and the slave-select input for the MSSP module. Obviously they had to trade
something for the capability. It would be nice if they had moved LVP to one
of the spare pins in the PLCC and QFP packages.

  - Tom

At 07:58 AM 10/24/99 +1000, Paul B. Webster wrote:
{Quote hidden}

------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

1999\10\24@120350 by Dwayne Reid

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>  It appears to be a truly amazing extension of their design psychosis;
>like saying you shouldn't use OPTION and TRIS instructions which *are*
>still perfectly valid on this processor but won't work on the only truly
>byte-wide port remaining, where you probably most *NEED* to use TRIS!
>
>  (Or will it?)

As far as I know, TRIS works only on ports 5,6,7 (A,B,C).  So sad . . .

I really would have preferred them to have used port A (its already
incomplete - whats one more bit).

dwayne


Dwayne Reid   <dwaynerspamKILLspamplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax

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