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'Jitter free TMR0 interrupt timing - Isn't it?'
1999\10\26@104332 by Jim Hartmann

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PIC TMR0 interrupt is jitter free is it not?  The documentation says the
interrupt latency is the same for 1 or 2 cycle instructions.

1999\10\27@202608 by Thomas Brandon

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You are correct about that, but the following section of the 16F87x sums it
up:
For external interrupt events, such as the INT pin or PORTB change
interrupt, the interrupt latency will be three or four instruction cycles.
The exact latency depends when the interrupt event occurs. The latency is
the same for one or two cycle instructions.

So you are correct in that 2 cycle instructions don't effect it, but the Q
cycle of the external event does. The basic thing is the PIC is polling the
interrupt pending bits every instruction cycle at a certain Q cycle, hence
depending on what Q cycle the event occurs in the delay is different (i.e.
there's jitter). The Scenix's avoid this by adding a delay to synchronise
external interrupts. Not quite sure of the details but they have a
deterministic delay. It does of course vary based on whether turbo mode is
enabled. With turbo mode (executes the 4 Q cycles in parallel allowing 1
instruction per clock cycle, but lengthening branches as pipeline must
clear) there is a 5 instruction cycle (= 5 clo0ck cycle delay) on external
interrupts. 2 inst. cycles to synchronise the interrupt, 3 to get to the
interrupt vector, internal interrupts have a 3 cycle delay.

Tom.
----- Original Message -----
From: Jim Hartmann <spam_OUTJim_hartmannTakeThisOuTspamSILENTKNIGHT.COM>
To: <.....PICLISTKILLspamspam@spam@MITVMA.MIT.EDU>
Sent: Wednesday, October 27, 1999 12:41 AM
Subject: Re: Jitter free TMR0 interrupt timing - Isn't it?


> PIC TMR0 interrupt is jitter free is it not?  The documentation says the
> interrupt latency is the same for 1 or 2 cycle instructions.

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