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PICList Thread
'Interrupt latency'
1996\09\23@011723 by Steve Hardy

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Does anyone have a definitive answer for the following?

If the PIC16CXX is executing a goto, the manual states that the
CPU executes an internal NOP in place of the following instruction
which was prefetched (but not executed).

When an interrupt occurs, it could interrupt the goto in one of two
places: during the fetch of the goto or during the execution of the
NOP.

Alternatively, the architecture could block the interrupt until the
NOP is completed.

The first case implies that when the interrupt returns, it could
execute the pending NOP.  The second implies that an interrupt can
be delayed by up to one instruction cycle.  What actually happens?

The answer has implications for using the PIC as a clock generator.
E.g. assume TMR0 is set to interrupt every 256 instruction cycles.
Now if the mainline code is simply

loop    nop
       goto    loop

then, since the interrupt will occur at each one of 3 points (nop,
goto fetch, implicit nop) then the interrupt routine's timing may
exhibit subharmonics of the 256-cycle basic timing (i.e. 1 cycle
jitter) if the second alternative is actually implemented.  There
would be no jitter with the first alternative.

I have looked on an oscilloscope, but can't see any jitter; but then
again perhaps the 'scope's resolution isn't good enough (it's an old
20MHz analogue).

Regards,
SJH
Canberra, Australia

1996\09\23@100049 by John Payson

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> Does anyone have a definitive answer for the following?
>
> If the PIC16CXX is executing a goto, the manual states that the
> CPU executes an internal NOP in place of the following instruction
> which was prefetched (but not executed).
>
> When an interrupt occurs, it could interrupt the goto in one of two
> places: during the fetch of the goto or during the execution of the
> NOP.
>
> Alternatively, the architecture could block the interrupt until the
> NOP is completed.

According to my understanding of the documentation, the first cycle follow-
ing an interrupt will either be a "skip" cycle [if the instruction just
executed was a skip] which advances the PC or a "dummy" cycle which does
not.  While the latency between the interrupt triggering and it being taken
will be constant, the total time taken by the interrupt may not; in prac-
tice this will almost never be an issue.

1996\09\23@184612 by TONY NIXON 54964

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I can't see that any interupt latency would matter on a simple clock.
The TMR0 IRQ bit will always be set every 256 cycles. Whether an
extra instruction, or not, is executed with the IRQ code does not
matter, as long as all the code fits into the IRQ timing space.
It's the same as trying to get the secs, mins and hours to update
simultaneously for the sake of accuracy. This of course can't be done
with a single processor, but it works fine anyway.

Regards

Tony


Just when I thought I knew it all,
I learned that I didn't.

1996\09\23@213417 by Steve Hardy

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> From: TONY NIXON 54964 <spam_OUTAnthony.nixonTakeThisOuTspameng.monash.edu.au>
>
> I can't see that any interupt latency would matter on a simple clock.
> The TMR0 IRQ bit will always be set every 256 cycles. Whether an
> extra instruction, or not, is executed with the IRQ code does not
> matter, as long as all the code fits into the IRQ timing space.
>  It's the same as trying to get the secs, mins and hours to update
> simultaneously for the sake of accuracy. This of course can't be done
> with a single processor, but it works fine anyway.

This is true, but not only is the clock expected to have an average period
of 256 cycles, in this application it must also have a consistent cycle-to-
cycle period of _exactly_ 256 cycles.  This may not occur if the interrupt
latency is variable.

To clarify: suppose the average rate is 1000Hz (exactly).  Now suppose
every third interrupt has an extra cycle of latency (say 1us).  Then the
sequence of timings between each pulse is then

  1000us  1001us  999us

Fourier analysis would reveal small but significant harmonic content at
333.333 Hz.

John Payson <.....supercatKILLspamspam@spam@mcs.net> says that there is in fact constant latency
in the PIC.  This is goodness.

Regards,
SJH
Canberra, Australia

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