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'Interrupt handling'
1996\05\16@141511 by Mike Jones

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Apologies in advance for this question. I know I should RTFM, but I
haven't been able to lay my hands on any manuals [ BTW - does anyone
know if there are any suppliers in the UK who still have the
Embedded Control Handbook and/or the Beginner's Guide to PIC
programming still in stock? - it's been on back order at my local
branch of Maplin for _months_ ]. Anyway, here's my question:-

How do I implement an interrupt service routine (particularly for
the PIC16C84, but I guess it's roughly the same for the other
devices)? I've tried putting the address of the routine at 0x04, but
the results seem to be unpredictable - sometimes the interrupt
causes a branch (sometimes to the interrupt server, sometimes
somewhere wildly different...), and returns don't always go back to
where I think they should.

What am I doing wrong?

TIA for any help....

Mike



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Mike Jones.        || e-mail (home) spam_OUTmikeTakeThisOuTspamnewjay.win-uk.net
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I thought PCs were a pain in the DOS, till I discovered Linux...
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'Interrupt handling'
1998\10\14@150559 by Gabriel Caffese
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Hi all,

Does anyone know how many interrupts/second a 586DX/133 (or other
processor) can handle ?

       Gabriel.-

1998\10\14@152507 by WF AUTOMACAO

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Gabriel Caffese wrote:
>
> Hi all,
>
> Does anyone know how many interrupts/second a 586DX/133 (or other
>  processor) can handle ?
>
>         Gabriel.-

Are you talking about the about a PC?

You can program the INT 8 of PC, for occurs 1.19mhz/x (where x=0..65535)
times!

Miguel.

1998\10\14@163407 by Peter L. Peres

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> Gabriel Caffese wrote:
> >
> > Hi all,
> >
> > Does anyone know how many interrupts/second a 586DX/133 (or other
> >  processor) can handle ?
> >
> >         Gabriel.-

A PC running a mainstream OS (hrrmph) can just barely manage 250 usec
interrupts with a 80% probability to crash your app and/or the OS within
the 1st 1000 msecs of doing this. Under severely hacked Unices 50 usec
seems to be the limit I've seen for short periods of time (= 20,000
interrupts per second) .

A processor can handle interrupts at a certain rate that can be
calculated. Assuming 1 task and 1 interrupt source, and a context switch
time of Tsw the total time to make 2 context switches (in and out of an
ISR) = 2 * Tsw.  Then you can achieve an interrupt rate such that the task
switching cost is at most 33% load (extreme case). Thus 3 * 2 * Tsw * N =
MAX. MAX is the processor MIPS (roughly), Tsw is the context switch in
Instructions (corrected for MIPS if req.), and N is what you want, the
number of interrupts per second you can reach at 33% load for task
switching only. Or:

N = MAX / ( 6 * Tsw )

It is instructive to put figures in this formula for real (measured) and
PubRel MIPS ratings for various vendors and processors ;) I did that with
some 8-bit micros ;) If you report this to the clock speed, the PIC is way
way high up in the list. (the PIC interrupt enable idiosyncrasies being
neglected)

Peter

PS: The forumla above is a rule-of-thumb method that seems to serve me
well. It means nothing else. 33% is a nice democratic number ;)

1998\10\14@181404 by William Chops Westfield

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   A processor can handle interrupts at a certain rate that can be
   calculated. Assuming 1 task and 1 interrupt source, and a context switch
   time of Tsw the total time to make 2 context switches (in and out of an
   ISR) = 2 * Tsw.  ...  N = MAX / ( 6 * Tsw )

It gets more complicated than that on fancy processors, since it is
difficult to predict the exact "cost" of an interrupt with respect to
instruction, data, and pager caches...

BillW

1998\10\15@124728 by Peter L. Peres

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On Wed, 14 Oct 1998, William Chops Westfield wrote:

>     A processor can handle interrupts at a certain rate that can be
>     calculated. Assuming 1 task and 1 interrupt source, and a context switch
>     time of Tsw the total time to make 2 context switches (in and out of an
>     ISR) = 2 * Tsw.  ...  N = MAX / ( 6 * Tsw )
>
> It gets more complicated than that on fancy processors, since it is
> difficult to predict the exact "cost" of an interrupt with respect to
> instruction, data, and pager caches...

Actually, the forumla is surprisingly accurate. It can be tested using a
simple assembly program doing just that (and indeally running entirely
inside the cache). What you are saying is, that it is complicated to
calculate a 'dry' figure for Tsw on complex machines. This is true, and
experiment and measurements are required.

Peter

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