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'Interfacing SRAM to 16C74A'
1998\03\03@062427 by Adrian Gothard

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I intend to interface an SRAM using 3 or 4 bits of Port A (RA0,1,2,5) as
A15:17, RC0:5 as A8:15, Port D as D0:7, and RE0:3 for CS, OE, and WR.

The first lash-up will use a 6116, moving on to the biggest SRAM for which
I have enough i/o lines. It'll be battery backed.

I've half-seriously considered serial-flash but don't want to suffer the
erase time periodically since RS232 data is coming in on other Port A bits
(software UART) and going out on RC6:7 (hardware UART) most of the time.

Has anyone done something similar before?
Comments?

Regards

Adrian

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Developers of GPS satellite-based tracking systems

1998\03\03@104013 by Alexandre Guimaraes

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   There are some serial Flash memories that have a dual buffering scheme.
This way you can erasing a block while you put the other one in the buffer,
this way you can cope with data that is coming in while saving the data that
has already come. One maker that has this kind of buffering scheme is
Nexcom. I think Nu-horizons os the distributor.

Best regards,
Alexandre Guimaraes
Microset Eletronica Ltda




>I've half-seriously considered serial-flash but don't want to suffer the
>erase time periodically since RS232 data is coming in on other Port A bits
>(software UART) and going out on RC6:7 (hardware UART) most of the time.
>

1998\03\03@125533 by Matt Bonner

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Adrian Gothard wrote:
>
> I intend to interface an SRAM using 3 or 4 bits of Port A (RA0,1,2,5) as
> A15:17, RC0:5 as A8:15, Port D as D0:7, and RE0:3 for CS, OE, and WR.
>
> The first lash-up will use a 6116, moving on to the biggest SRAM for which
> I have enough i/o lines. It'll be battery backed.
>
> I've half-seriously considered serial-flash but don't want to suffer the
> erase time periodically since RS232 data is coming in on other Port A bits
> (software UART) and going out on RC6:7 (hardware UART) most of the time.
>
> Has anyone done something similar before?

I've interfaced a '74A to 2 4Mbit parallel EEPROMS.  Microchip has an
app note on bit-banging higher density memories, but it's really not
that difficult.  Just keep track of your "page" - the page address is
simply everything above A15.

--Matt

1998\03\03@125537 by Harold Hallikainen

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On Tue, 3 Mar 1998 06:24:27 -0500 Adrian Gothard <.....whdKILLspamspam@spam@ZETNET.CO.UK>
writes:
>I intend to interface an SRAM using 3 or 4 bits of Port A (RA0,1,2,5)
>as
>A15:17, RC0:5 as A8:15, Port D as D0:7, and RE0:3 for CS, OE, and WR.
>


       Do you really need to drive CS?  Seems that the chip could always
be enabled.  Also, I've got several products using the Dallas RamPort,
which is 2 K bytes.  It uses 8 data bits, but repeats them on the other
side of the chip, plus three control lines.  So you really only lose 3
i/o pins.  It'd be nice to have have a big static ram in an 8 pin package
on SPI or I2C, but I haven't found it yet.  Meanwhile... I've been buying
lotsa Dallas parts!

Harold



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1998\03\04@101433 by Tom Handley
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  Adrian, I have a couple of 16C74A projects that use external SRAM with
built-in Clock/Calendars. Check out Dallas Semiconductor products if you
are interested in combined SRAM, RTCC, Crystal, and Battery. I use Port E
and D as you described. In one project I use a 512KByte Dallas SRAM/RTCC
with an external address decoder and address latches. In another I use a
version that multiplexes the address and data lines. They have several
such devices. In addition to RD/WR/CS, you need ALE (Address Latch Enable)
and upper/lower address strobe inputs. You can get them with or without
internal clocks and batteries.

  - Tom

At 06:24 AM 3/3/98 -0500, you wrote:
{Quote hidden}

1998\03\04@140339 by Adrian Gothard

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Have you any code to spare?
(Might speed me up a bit)

I'm looking at the Samsung 681000 and also the Hitachi 628128 128kb x 8
devices at the moment.



At 07:12 04/03/98 -0800, you wrote:
{Quote hidden}

Regards

Adrian

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---
Developers of GPS satellite-based tracking systems

1998\03\06@085506 by Tom Handley

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  Adrian, the code would depend on which SRAM you are using. Once you
decide on a chip (serial, parallel, or multiplexed address/data bus)
then I can help. It really is simple. You are not using Ports D and E
in the slave mode but are bit-banging port E to provide CS, RD, and WD.
You can use port A or B lines to provide external control signals such
as latch/address-enable, address strobe/s, etc. If you use the Dallas
chips with RTCCs, the clock registers are stored at the top of RAM
space.

  For a standard 128K x 8 SRAM, you need 17 bits. You could use two
external 8-Bit latches and 1 port A pin. This would require 2 latch-
enable signals from, say Port A. I don't know what resources you have
available. If port B is available, you could get by with 1 latch and 1
enable from port A. This would allow something like using port B for
A0-7, external latch for A8-15, and port A for A16. In my case, with
the 512KByte device, I use 2 external latches and 3 port A lines. I
look at it as 8 banks of 65K from a software standpoint. In your case,
maintain a 16 Bit counter and if it overflows, set the port A Bit (A16).

  - Tom

At 02:03 PM 3/4/98 -0500, you wrote:
{Quote hidden}

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