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'IDEA about Microchip vs. Scenix'
1997\11\16@183949 by johnb

picon face
J.Adams wrote:
>
> Scenix will have a better, faster product. Maybe it will scare Microchip into
> advancing faster.
************************************
There is an article in the UK journal Electronics Weekly Nov. 5th 1997
about Microchip. It quotes Steve Sanghi (Arizona CEO) as saying
"everybody likes fast peripherals". He is talking specifically about the
new 16C1xx series. The article states that "this belief has led
Microchip to an unusual clock strategy for the 16C1xx series. The 10MHz
crystal oscillator feeds an on-chip 40MHz phase-locked loop (PPL). This
drives the peripherals directly, and the core at 10MHz through a
divide-by-four".

The "divide-by-four" is used to get really clean waveforms in many
processors. To quote the 16C84 Data Sheet:

"The clock input (from OSC1) is internally divided by four to generate
four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4.
Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and latched into the
instruction register in Q4. The instruction is decoded and executed
during the following Q1 through Q4."

The proposed Microchip method does it without using a crystal of 4 times
the instruction frequency (which would use more power). What worries me
is that PPLs are tricky things to stabilise; I hope the Microchip method
is "completely transparent to the user".

Some may remember the 6502, which had a one microsecond instruction
cycle when using a 1-MHz clock. It relied on nanosecond delays inside
the chip to generate non-overlapping internal phi-1 and phi-2 clocks. It
was highly sensitive to power-line interference, and the 4 MHz versions
were worse. I hope the Scenix doesn't work like this. It should be much
better, of course - this is 1997, and the 6502 is jurassic by
comparison. When Rockwell made a 6502 with a divide-by-four system,
everything was fine.

The proposed Microchip strategy would be VERY interesting if they
incorporate a feature that I haven't seen mentioned - that the PPL
division ratio could be PROGRAMMABLE. This way, you could change the
clock frequency (and therefore the power consumption) on the fly. For
example, a 32768 Hz clock could be used, with a X400 division ratio,
giving a clock of 3.2768 MHz for fast processing. For low-power use
change the division ratio to X4 and the clock will then be 32768 KHz.
And you can use special division ratios to get any frequency that is
needed - for a specific baud-rate, for example.

This could be done with a 16Cxx chip NOW. But it needs support chips
(HC4046 PPL and some frequency dividers), and PIC-chips are supposed to
be a 1-chip solution. If it were on-chip it would be practical.

Mitsubishi still make various versions of the 6502. The 50734 was
attractive - 32 I/O pins including complete Centronics printer I/P port,
5 timers, 4-channel 8-bit A/D, PWM O/P, UART with baud-rate generator,
synchronous serial I/O, dual stepper-motor O/P, 11 interrupts (5
vectored), supports 128K RAM/ROM. And all in a 64-pin shrink-DIP...

John Blackburn,
South London UK.

1997\11\16@191922 by William Chops Westfield

face picon face
   The proposed Microchip strategy would be VERY interesting if they
   incorporate a feature that I haven't seen mentioned - that the PPL
   division ratio could be PROGRAMMABLE. This way, you could change the
   clock frequency (and therefore the power consumption) on the fly. For
   example, a 32768 Hz clock could be used, with a X400 division ratio,
   giving a clock of 3.2768 MHz for fast processing. For low-power use
   change the division ratio to X4 and the clock will then be 32768 KHz.
   And you can use special division ratios to get any frequency that is
   needed - for a specific baud-rate, for example.

Higher end Motarola "microcontrollers" (ie 68331) do this.  The clock ends
up with somewhat questionable stability, if you're using it for timing
purposes, I think.  At least, our old 68331 based product was cursed by or
Network Time Protocol wizards as being the only box whose timer (based on
32768 Hz crystal) wasn't stable enough to be a credible NTP system...


   Some may remember the 6502, which had a one microsecond instruction
   cycle when using a 1-MHz clock. It relied on nanosecond delays inside
   the chip to generate non-overlapping internal phi-1 and phi-2 clocks.

Have you seen some of the research peeking its head out concerning processor
based on totally Asynchronous designs (no clock!)  Mind boggling...

BillW
cisco

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