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'External ram....'
1998\12\20@065716 by Mark J Anstice

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Hi all,

I have a (common?) question.  I need to interface a PIC with a RAM chip.  The
RAM chips data (positional information for servos) needs to be written to via
RS232 protocol (from a PC).  I have seen a few designs for interfacing PIC's
to RAM but there aren't enough IO lines leftover (8 spare lines would be ideal
as these are to be connected to servos).  If possible, I would like to use the
16C84 or the newer 16F84.

Thanks in advance,

Mark.

1998\12\20@104638 by White Horse Design

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At 11:45 20/12/98 , Mark J Anstice wrote:

>I have a (common?) question.  I need to interface a PIC with a RAM chip.  The

I do this with a 16C74 (has a uart) to a 128kbyte SRAM though it has enough
i/o lines to address a higher capacity part.

Regards

Adrian
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1998\12\20@121216 by dave vanhorn

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At 06:45 AM 12/20/98 -0500, you wrote:
>Hi all,
>
>I have a (common?) question.  I need to interface a PIC with a RAM chip.  The
>RAM chips data (positional information for servos) needs to be written to via
>RS232 protocol (from a PC).  I have seen a few designs for interfacing PIC's
>to RAM but there aren't enough IO lines leftover (8 spare lines would be ideal
>as these are to be connected to servos).  If possible, I would like to use the
>16C84 or the newer 16F84.


I've got that written in Atmel AVR8515, including storing servo positions
in (internal) ram.
http://www.dontronics.com download dungeon, "getting started" code.
Beware, the 1-2mS width standard isn't. I found brand new Cirrus servos
that wanted 400uS to 2mS for full travel. Futabas are 1-2mS, I haven't
tested others.


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1998\12\20@150034 by Harold M Hallikainen

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On Sun, 20 Dec 1998 15:39:34 +0000 White Horse Design <.....whdKILLspamspam@spam@ZETNET.CO.UK>
writes:
>At 11:45 20/12/98 , Mark J Anstice wrote:
>
>>I have a (common?) question.  I need to interface a PIC with a RAM
>chip.  The
>
>I do this with a 16C74 (has a uart) to a 128kbyte SRAM though it has
>enough
>i/o lines to address a higher capacity part.
>


       As previously mentioned, I'm using the Dallas RamPort chips to get 2
Kybytes of ram added to a 16c74a.  I use the normal RamPort in some
products and the battry backed one in others.
       I'm now looking at going with a 128 Kbyte external battery backed RAM on
the 16c74a without chewing up all the I/O pins.  Since serial SRAMs don't
seem to be available, I WAS considering using shift registers to clock
out the address and another 8 pins for data I/O.  As someone on the list
pointed out, since I have the 8 bit "databus", I may as well use it for
everything.  So, current plan is to put a couple octal latches on the
same pins connected to the RAM data lines.  A couple more PIC pins will
act as "chip selects" for these, and I can then output a 16 bit address.
I can also hang an LCD module on the same databus.
       I think there's a limit to how much we can economically expand a
microcontroller.  Again, the ideal design has zero parts, and it'd be
great to have micro designs with one part: the microcontroller.  Piling a
bunch of stuff around it, we may as well go to a microprocessor instead
of a microcontroller.  At some point, this becomes a lower cost approach.
Want more ROM?  Hang it on the bus!  Want more RAM?  Hang it on the bus!
Want more I/O?  Hang it on the bus!


Harold

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1998\12\20@164002 by paulb

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Mark J Anstice wrote:

> 8 spare lines would be ideal as these are to be connected to servos.

 Bear in mind that you *only* use bare PIC lines to drive servos in a
single-chip unit.  The "expander" chip to drive ten servos from two
lines is a (HC)4017, as used in R/C receivers.
--
 Cheers,
       Paul B.

1998\12\21@071646 by Tom Handley

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  Adrian, I designed an SRAM controller for the PIC16C74A/77 using a
Lattice ispLSI1016E CPLD. It requires a chip-select, 8 data lines, and 3
state-select lines. I use RE2, Port D, and RA0-2. It provides 19 address
lines and 5 external chip-selects or latch-enables. It supports 32KB, 128KB,
and 512KB SRAMs in a standard 32-pin socket. The 1016E comes in a 44-pin
PLCC package.

  The first 3 states load the address latches. The other 5 states provide
chips selects and latch-enables for expansion. I'm about done testing this
and I'll put it on my web site when it's finished. I also have a Lattice
ispLSI CPLD programmer that can be built for free depending on what folks
have in stock. I provide the isp stream file.

  I had originally built this in support of my PIC-based logic analyzer
which is in prototype. I decided to make a versatile proto board using
microEngineering Labs' PICProto64 board. The board has a 40 pin ZIF socket,
the 1016E CPLD, a 32-pin SRAM socket, a 74C922 keypad encoder, MAX232A
RS232, an SPI-style interface, and an LCD interface. There are a variety of
jumpers to configure all the peripherals. I'll also put that on my web site
when it's done. I'm testing it right now with the CPLD.

  - Tom

At 03:39 PM 12/20/98 +0000, Adrian Gothard wrote:
>At 11:45 20/12/98 , Mark J Anstice wrote:
>
>>I have a (common?) question.  I need to interface a PIC with a RAM chip.
The
{Quote hidden}

1998\12\24@123640 by John Payson

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|        I think there's a limit to how much we can economically expand a
|microcontroller.  Again, the ideal design has zero parts, and it'd be
|great to have micro designs with one part: the microcontroller.  Piling a
|bunch of stuff around it, we may as well go to a microprocessor instead
|of a microcontroller.  At some point, this becomes a lower cost approach.
| Want more ROM?  Hang it on the bus!  Want more RAM?  Hang it on the bus!
| Want more I/O?  Hang it on the bus!

One advantage a microcontroller has, though, over a microprocessor
is that the code-space address and data buses are "sheltered".  On
a microprocessor-based system, any sort of fault on the address or
data bus will totally hose system operation, but a suitably-design-
ed microcontroller-based system may be able to detect the fault and
either attempt to recover (if the fault is transient) or diagnose
and report the condition (if it's persistent).

On one microcontroller system I designed which used external RAM for
data storage (but ran code internally) I had a CPU burned with test
code which would output a unique sequence of pulses on all of the
port pins.  Thus, troubleshooting boards was a simple matter of scop-
ing all points on the board until I found one whose pattern was not
as it should be.  I then knew that that pin was either open or short-
ed to something.  Looking at the corresponding signal on the CPU
would tell me which.

By contrast, if that had been a microprocessor-based system, all I
would have been able to see was that it wasn't working and was run-
ning seemingly-random code.  Finding the specific fault and fixing
it would have thus been much more difficult.

1998\12\24@141956 by Keith M. Wheeler

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Another added benefit of a "sheltered" bus:  less radiated noise.  I've
seen one design where the controller chosen was overkill (a 17C756),
but it had all of what was needed (and more) on board, so there would
be no pesky data lines snapping up and down.

-Keith Wheeler
ARMA Design                             http://www.ARMAnet.com/


At 11:33 AM 12/24/98 -0600, John Payson wrote:
{Quote hidden}


'External ram....'
1999\01\04@073626 by ebos
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Mark J Anstice wrote:

> Hi all,
>
> I have a (common?) question.  I need to interface a PIC with a RAM chip.  The
> RAM chips data (positional information for servos) needs to be written to via
> RS232 protocol (from a PC).  I have seen a few designs for interfacing PIC's
> to RAM but there aren't enough IO lines leftover (8 spare lines would be ideal
> as these are to be connected to servos).  If possible, I would like to use the
> 16C84 or the newer 16F84.
>
> Thanks in advance,
>
> Mark.

What about I2C RAM's     Type    24c64

Eduard Bos

1999\01\04@090330 by keithh

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Mark J Anstice wrote:

> I need to interface a PIC with a RAM chip...
> there aren't enough IO lines leftover

Serial RAM (I2C or SPI) is one option.

How about DRAM chips?
Each address line is used twice, thus a 4164 (64Kx1bit)
uses only 8 address lines not 16.
You don't have to use, or refresh, _all_ the DRAM locations.

You can pick up an old PC memory board full of 41256
chips for a few bucks from a computer junk box at
computer fair stands.

Some DRAM chips (e.g. 4464 = 64Kx4) have an /OE pin,
so after latching out the row and column address you can
set the address lines to inputs for reading the
data pins!

Thus you can use 12 pins (MA0-7,/WE,/RAS,/CAS,/OE)
to read/write 64K bytes from two 64Kx4 chips!

Cunning huh?

Maybe faster than an I2C chips too.

1999\01\04@215456 by Mike Keitz

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On Mon, 4 Jan 1999 14:04:50 +0000 Keith Howell <.....keithhKILLspamspam.....arcam.co.uk>
writes:

>Some DRAM chips (e.g. 4464 = 64Kx4) have an /OE pin,
>so after latching out the row and column address you can
>set the address lines to inputs for reading the
>data pins!

That's a really cool idea.  The 256Kx4 and 1Mx4 chips also have OE, I
guess anything x4 does because the same data pins serve for in and out.
Four-bit wide DRAMS are commonly found on video cards.
>
>Thus you can use 12 pins (MA0-7,/WE,/RAS,/CAS,/OE)
>to read/write 64K bytes from two 64Kx4 chips!

If you're accessing the data somewhat sequentially, another major trick
I've done is to use the internal refresh counter to supply row addresses.
To do that, execute a CAS-before-RAS refresh cycle, then hold RAS low
and apply a pulse to CAS to latch a column address from the address pins
and segeue into a page-mode cycle.   This kind of operation is officially
endorsed as a means to test the refresh counter.  Since the address pins
don't need to be multiplexed, it's easy to use an external counter or
shift register to drive them.

There's no way to reset the refresh counter, so you need to keep track of
how many CAS before RAS cycles have been executed.  If you're using a x1
chip, only half of the chip can be used (e.g. with the 256Kx1, the
address counter is only 8 bits wide, so you get 256 x 512).  The x4 chips
it looks like this trick could access all bits.  Also no 64K chips and
only some 256K chips support the CAS-before-RAS mode.

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1999\01\06@023545 by Dr. Imre Bartfai

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On Mon, 4 Jan 1999, ebos wrote:

> Mark J Anstice wrote:
>
> > Hi all,
> >
> > I have a (common?) question.  I need to interface a PIC with a RAM chip.  Th
e
> > RAM chips data (positional information for servos) needs to be written to vi
a
> > RS232 protocol (from a PC).  I have seen a few designs for interfacing PIC's
> > to RAM but there aren't enough IO lines leftover (8 spare lines would be ide
al
> > as these are to be connected to servos).  If possible, I would like to use t
he
{Quote hidden}

Hi,
AFAIK 24C64 is an EEPROM. The potential problem is, the
writing/programming time is about 5 (max 10) msec. I have similar problem.
Obviously there is a PCF8570 from Philips, but it has limited capacity
(256 bytes). Otherwise, one should use (maybe with an I/F circuit) a
parallel static RAM.
Imre

1999\01\06@132024 by

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{Quote hidden}

1999\01\09@185606 by Mark J Anstice

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I have been delving more into the interfacing to a ram chip, a serial EEPROM
may be one of the best solutions, as I have seen a device from Microchip that
can store 64K. Myke Predko's book "Programming and customizing the PIC
micocontroller" contains a project that controls four servos and a LCD with a
serial EEPROM for positional/command info.

Of course, the fewer IO pins dedicated to storing/retrieving data from a ram
chip, the more IO pins left over for sensors etc.

I'd like to take this opportunity to thank Paul B for his 4017 chip suggestion
for expanding the number of servos, very tidy.

By the way, my coding at the moment hasn't progressed from the MPLAB
simulation phase as I'm still looking for a decent PIC programmer.  I'm
considering purchasing the PICSTART Plus from Microchip as I'll be able to
develop applications for the whole? range of microcontrollers - Also my
hardware design changes on a daily basis!.  I've seen lots of programmer
devices for the 16C84, but my design requires RS232  capability which is built
into the 16C74 & 16C64 micros.  I've seen plenty of code to implement RS232 in
software with a 16C84 which is electrically erasable - very good from a re-
programming point of view.  I've now come to realise that there are soooooo
many alternatives and trade-offs in PIC development in both the hardware and
software aspects, you could spend eternity thinking about the 'better'
solution.  Anyway, I must do some more research!!!!


Mark.

1999\01\10@072117 by Andy Kunz

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>By the way, my coding at the moment hasn't progressed from the MPLAB
>simulation phase as I'm still looking for a decent PIC programmer.  I'm

Consider the Carmacon upgrade to the Parallax programmer.  It supports
RS-232 under Win3.1, Win95, and WinNT.

Andy



==================================================================
 Andy Kunz - Montana Design - http://www.users.fast.net/~montana
==================================================================

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