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'Disable Interupts While Accessing Bank 1,2,3 Ram ?'
2000\04\21@003734 by John Fisher

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While troubleshooting some code tonight I realized that maybe you need to
disable interrupts while accessing banks 1,2 or 3. I noticed that the
standard interrupt template saves off 'w' and 'status' in what it expects to
be bank 0. If I'm using bank 1,2 or 3 this is not cool with unexpected
results. The whole problem showed up when I started using 'banksel'.
Eventually I gave up and crammed everything into bank 0. Maybe it's a bank
switching problem or maybe it's an interrupt problem. But it works now that
I have given up the other 3 banks. There must be a better way to handle
things on the '877. If you have to banksel and disable interrupts for every
access above bank 0, there must be a better way :-)

Regards,
John

=============================================
email:     spam_OUTjfisher2TakeThisOuTspamaustin.rr.com
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callsign:  K5JHF
=============================================

2000\04\21@022306 by Dan Michaels

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John Fisher wrote:
>While troubleshooting some code tonight I realized that maybe you need to
>disable interrupts while accessing banks 1,2 or 3. I noticed that the
>standard interrupt template saves off 'w' and 'status' in what it expects to
>be bank 0. If I'm using bank 1,2 or 3 this is not cool with unexpected
>results. The whole problem showed up when I started using 'banksel'.
>Eventually I gave up and crammed everything into bank 0. Maybe it's a bank
>switching problem or maybe it's an interrupt problem. But it works now that
>I have given up the other 3 banks. There must be a better way to handle
>things on the '877. If you have to banksel and disable interrupts for every
>access above bank 0, there must be a better way :-)
>
>Regards,
>John
>

Same time zone - in case you are still hammering away [and everyone
else is snoozing], this has been a major bugaboo with PIC since day 2.
First instruction in the ISR is usually

       movwf   w_temp

which always plants the data into the "currently-selected" bank.
Setting STATUS to bank 0, for additional register saves occurs later
in the ISR.

The "usual" solution is to assign < w_temp > to a location that won't
do any harm when it is overwritten, IRREGARDLESS of the bank. In other
words, look at where the < w_temp > offset address resides in banks
0, 1, 2, etc, and realize the ISR doesn't know the difference. Make
sure your important data doesn't reside at that same offset in the
higher banks.

Making < w_temp > the 1st or last RAM location is a common way to
go. Also, due to the way the std ISR is written, < status_temp >
will normally write to bank 0 only.

[I am relating this, being familiar with the older 2nd gen PICs,
but not yet the '87x specifics - which I presume work the same
miserable way. If I am wrong, someone will no doubt correct this
tomorrow].

Hope this makes some sense, it's late, and goodnite,
- Dan Michaels

2000\04\21@022927 by Mike Morris

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<x-flowed>The simplest thing to do (for the '877) is define the context save register
for W in the upper 16 bytes of the GPRs since they are common to all 4
banks. Then it doesn't matter which bank you are in when you save W in your
interrupt service routine. If you don't use a location in the upper 16
bytes, then you have to make sure you allocate a 'w saving' register at the
same offset in all the banks, since you usually don't know which bank
you'll be in when an interrupt occurs. Interrupts while in any bank is no
problem as long as your context saving/restoring works properly. Just
follow the example in the '877 data sheet. Define w_temp in the upper 16
bytes of bank 0, and everything will work fine (well, as far as context
saving.  :)

- Mike

At 11:22 PM 4/20/2000 -0500, you wrote:
{Quote hidden}

</x-flowed>

2000\04\21@075758 by Thomas McGahee

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See the code example and explanation included in the file PICUART.ZIP
that you will find at:
http://mcgahee.freeservers.com

This shows how to handle the problem for two banks and how it can be
extended to more banks. It both explains the problem and offers a
simple solution.

The PICUART.ZIP file contains MANY other additional tidbits of
information related to using interrupts, UARTS, and other things.
If you haven't already gotten yourself a copy, do yourself a favor
and download it. It contains many items of interest that can save you
hours of time.

Fr. Tom McGahee

{Original Message removed}

2000\04\21@103835 by Kbek Tony

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Hi,

>While troubleshooting some code tonight I realized that maybe you need
to
>disable interrupts while accessing banks 1,2 or 3. I noticed that the
>standard interrupt template saves off 'w' and 'status' in what it
expects to
>be bank 0. If I'm using bank 1,2 or 3 this is not cool with unexpected
>results. The whole problem showed up when I started using 'banksel'.

Yep this could happen if you also dont save the pagebits, one way
to 'solve' it is by saving theese to something like:
( and remember that the save variables must be located at the same
ram positions in all banks, for 16F87x the ram that starts at location
0x070 bank0, 0x0F0 bank1, 0x170 bank2 and 0x1F0 bank3 )

Define your 'all bank variables' ( you only need to define (allocate)
them in one bank).

       ; *** Bank0/1/2/3 mirrored in all banks 0x70, 0xF0, 0x170,
0x1F0, 16 bytes
       CBLOCK  0x070
       ; ram variables accesible from all banks mainly used for context
saving
       ; ( ram area above 0x70 are mirrored in all banks )
       Saved_W:1       ; variable used for context saving
       Saved_Status:1  ; variable used for context saving
       Saved_Pclath:1  ;
       Saved_Fsr:1     ;
       ENDC

Then some handy macro's:
;+++++
;       PUSH/PULL save and restore W,PCLATH,STATUS and FSR registers -
;       used on interrupt entry/exit


PUSH    MACRO
       MOVWF   Saved_W         ; save w reg
       SWAPF   STATUS,W        ;The swapf instruction, unlike the movf,
affects NO status bits.
       CLRF    STATUS          ; sets to BANK0
       MOVWF   Saved_Status    ; save status reg
       MOVF    PCLATH,W
       MOVWF   Saved_Pclath    ; save pclath
       CLRF    PCLATH
       MOVF    FSR,W
       MOVWF   Saved_Fsr       ; save fsr reg
       ENDM

PULL    MACRO
       MOVF    Saved_Fsr,W     ; get saved fsr reg
       MOVWF   FSR             ; restore      
       MOVF    Saved_Pclath,W  ; get saved pclath
       MOVWF   PCLATH          ; restore
       SWAPF   Saved_Status,W  ; get saved status in w
       MOVWF   STATUS          ; restore status ( and bank )
       SWAPF   Saved_W,F       ; reload into self to set status bits
       SWAPF   Saved_W,W       ; and restore
       ENDM

And onto the ISR routine:

       ORG     0x004             ; interrupt vector location
       PUSH    ; save registers                
INT
               
       ; Interrupt code

INT_DO_SOMETHING

INT_EXIT
       PULL    ; restore registers
       RETFIE  ; return from interrupt

Then you should have no problems with the bank switching.
FSR might not need saving, all depends one if you use it outside int or
not.


/Tony


Tony KŸbek, Flintab AB            
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
E-mail: tony.kubekspamKILLspamflintab.com
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ

2000\04\21@110327 by John Fisher

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Thanks a million Dan, I appreciate your reply. I understand this approach
and will give it a try :-)

Regards,
John

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email:     .....jfisher2KILLspamspam.....austin.rr.com
web:       http://home.austin.rr.com/jfisher2
callsign:  K5JHF
=============================================

{Original Message removed}

2000\04\21@132618 by Tom Handley

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  Dan (and John), one of the nice things about the 16C76/77 and 16F876/877
devices is that the upper 16 Bytes are aliased to Bank 0. This is a good
place to keep a copy of W, STATUS, PCLATH, FSR, etc, during an ISR routine.

  - Tom

At 12:20 AM 4/21/00 -0600, Dan Michaels wrote:
{Quote hidden}

[snip]
>[I am relating this, being familiar with the older 2nd gen PICs,
>but not yet the '87x specifics - which I presume work the same
>miserable way. If I am wrong, someone will no doubt correct this
>tomorrow].
>
>Hope this makes some sense, it's late, and goodnite,
>- Dan Michael


------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

2000\04\21@134523 by Dwayne Reid

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<x-flowed>At 11:22 PM 4/20/00 -0500, John Fisher wrote:
>While troubleshooting some code tonight I realized that maybe you need to
>disable interrupts while accessing banks 1,2 or 3. I noticed that the
>standard interrupt template saves off 'w' and 'status' in what it expects to
>be bank 0. If I'm using bank 1,2 or 3 this is not cool with unexpected
>results.

Have a look at the uart code that Thomas McGahee posted on his site - it
shows one way to deal with the problem.  You have to reserve 1 byte on each
RAM page in the same relative position - I choose to use the 1st available
byte (0x20, 0xA0, 0x120, 0x1A0).  I call them WSAVE, WSAVE1, WSAVE2,
WSAVE3.  The ISR context save code stores W to the WSAVE reg on that
particular page, then gets status into W, forces ram page 0, then proceeds
to save status and all the rest of the registers at risk on page 0.  It
works like a charm!

Here is a snip from his code:

                org     h'0004'         ;interrupt vector location

inthandler                              ;global ints automatically disabled
on entry!
                                        ;first, save w and status so we
don't really
                                        ;mess up the system!
                movwf   savew           ;save w register! (at h'20',
h'A0', etc.)
                movf    status,w        ;w now has copy of status
                clrf    status          ;ensure we are in bank 0 now!
                movwf   savestatus      ;save status
                movf    pclath,w        ;save pclath
                movwf   savepclath      ;!!! SUBTLE GOTCHA !!! This one
doesn't
                                        ;bite you until you have code that
                                        ;crosses page boundaries. How
insidious!
                clrf    pclath          ;explicitly select Page 0

                movf    fsr,w
                movwf   savefsr         ;save fsr (just in case)

;its now safe to parse the interrupt flags and jump to the appropriate routine.

intclean
                movf    savefsr,w
                movwf   fsr             ;restore fsr

                movf    savepclath,w
                movwf   pclath          ;restore pclath. (Page=original)

                movf    savestatus,w
                movwf   status          ;restore status! (bank=original)
                                        ;also puts you back on the
starting ram page
                swapf   savew,f         ;restore w from *original* bank!
                swapf   savew,w         ;swapf does not affect any flags!


                retfie                  ;return from interrupt!
                                        ;gie is auto-re-enabled.




Dwayne Reid   <EraseMEdwaynerspam_OUTspamTakeThisOuTplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax

Celebrating 16 years of Engineering Innovation (1984 - 2000)

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Do NOT send unsolicited commercial email to this email address.
This message neither grants consent to receive unsolicited
commercial email nor is intended to solicit commercial email.

</x-flowed>

2000\04\21@135114 by Quitt, Walter

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w_temp and status_temp are both of type udata_share.
That means they are put into the unbanked file reg or ram space.
Quoting from the MPASM User's Guide with MPLINK and MPLIB:
"This directive is used to declare variables that are allocated
RAM that is shared across all RAM banks (i.e. unbanked RAM)."

My version of the standard template embodies itself as the following
non bank specific way:

INT_VECTOR      CODE    0x004   ; interrupt vector location
       nop                     ; worthless place saver for the
following..004

page0           CODE    0x005   ; page0 starts at 5 in 16f877i.inc

       ; *** Save the World ***
       movwf   w_temp          ; save off current W register contents
005
       movf    STATUS,w        ; move status register into W register
006
       movwf   status_temp     ; save off contents of STATUS register
007

       ; *** Process the Interrupt ***
       call    ISR             ;
008

       ; *** Restore the World ***
       movf    status_temp,w   ; retrieve copy of STATUS register
009
       movwf   STATUS          ; restore pre-isr STATUS register contents
00A
       swapf   w_temp,f        ;
00B
       swapf   w_temp,w        ; restore pre-isr W register contents
00C
       retfie                  ; return from interrupt
00D


{Original Message removed}

2000\04\21@135525 by Quitt, Walter

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Save the status reg.  It holds the bank bits RP0 and RP1.
Just like the example does in shared (unbanked) memory.

{Original Message removed}

2000\04\21@155821 by Dan Michaels

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At 10:13 AM 4/21/00 -0700, you wrote:
>   Dan (and John), one of the nice things about the 16C76/77 and 16F876/877
>devices is that the upper 16 Bytes are aliased to Bank 0. This is a good
>place to keep a copy of W, STATUS, PCLATH, FSR, etc, during an ISR routine.
>
>   - Tom
>

Yes, I forgot to remember in the middle of last nite, while contemplating
being asleep, that some of the *older* 2nd gen PICs [like '76] have RAM
shadow mapping. Definitely the way to go. Thanks, Tom.

I suspect, however, the new '873 still does it the old '73 way [ie,
no shadow mapping]. Yes/no/maybe ?????

- Dan

2000\04\21@165745 by Dwayne Reid

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<x-flowed>At 01:57 PM 4/21/00 -0600, Dan Michaels wrote:

>I suspect, however, the new '873 still does it the old '73 way [ie,
>no shadow mapping]. Yes/no/maybe ?????

Yes!  The '873, 874 do NOT shadow the upper 16 registers.  So you have to
do it the old fashioned way like I posted earlier.  Quite frankly, I'll
probably continue to do so when I graduate to the larger devices since that
shadowed RAM could be really useful elsewhere.

dwayne



Dwayne Reid   <dwaynerspamspam_OUTplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax

Celebrating 16 years of Engineering Innovation (1984 - 2000)

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Do NOT send unsolicited commercial email to this email address.
This message neither grants consent to receive unsolicited
commercial email nor is intended to solicit commercial email.

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