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'DRAM with battery backup'
1998\03\11@233135 by Danjel McGougan

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Hi all,

First of all I want to thank everyone who answered my mail concerning
audio compression algorithms. They were really helpful and now I have
a general idea of how to proceed.

For those of you who didn't read the mail: I'm thinking of building a
digital telephone answering machine and needed some help in deciding
what type of memory and software compression to use for storing the
speech.

I'm going the hard way without the use of ISD's chips. I'm
thinking of using a 2M x 4 DRAM chip for storing 4-bit ADPCM codes at
6kHz sampling frequency. This gives me approximately 6 minutes of
speech with reasonable quality which ought to be enough.

I've written ADPCM decoding and encoding routines and found that I
need about 110 program cycles per sample to encode and about 80
program cycles to decode. With overhead I'll probably need a crystal
running at 8MHz.

Now to the problem. I need to use DRAM which I have very little
experience in using (I'm really a software guy, not hardware). How
does one proceed to design a battery backed-up system with a DRAM and
a PIC processor? I understand that the DRAM must go into self-refresh
mode when the power is cut. Also, how do I get the memory to refresh
during normal operation? I understand that I probably need some kind
of external counter and perhaps something else to run the refreshing.
I'd really appreciate ideas and schematics for solving some of these
problems or all of them :-)

Thanks in advance,
Danjel McGougan.

1998\03\12@003207 by Mike Keitz

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On Thu, 12 Mar 1998 05:30:38 +0000 Danjel McGougan
<spam_OUTdanmc458TakeThisOuTspamSTUDENT.LIU.SE> writes:

>Now to the problem. I need to use DRAM which I have very little
>experience in using (I'm really a software guy, not hardware). How
>does one proceed to design a battery backed-up system with a DRAM and
>a PIC processor? I understand that the DRAM must go into self-refresh
>mode when the power is cut. Also, how do I get the memory to refresh
>during normal operation? I understand that I probably need some kind
>of external counter and perhaps something else to run the refreshing.

You really need to RTFM on the RAM chip you intend to use, since there
are several different kinds.  At the very least, it'll support
CAS-before-RAS refreshing.  This means you can keep the data in the DRAM
alive just by holding all the pins except RAS and maybe WE low, and hae
your PIC or an external timer apply periodic (about 30 KHz) short low
pulses to RAS.  The DRAM chip contains an internal counter that will
sequence through all the rows for you.  Maybe "self-refresh" involves an
internal timer as well, I'm not familiar with that.

When power is on, you can do CAS-before-RAS cycles periodically,
interspersed with your data reading or writing cycles if the machine is
active.

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1998\03\12@120503 by andre

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Speaking of DRAM what I can recommend you is to use RAM
with EEPROM build in it. every thing is inside when you power it on
it will automatically load data from eeprom when you turn it off
it will automatically load data to eeprom. I played with it it is
very good toy but it is more expensive.
if you need to try I can look for the name. I have a data book.

Andre

Danjel McGougan wrote:

{Quote hidden}

--








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= http://www.compufire.com               =
= .....andreKILLspamspam@spam@compufire.com             =
= mcu-engineeringspamKILLspamcompufire.com   =
= Andre Abelian: Engine Electronics, Inc.=
= Tel 909-589-5485  Fax 909-598-5695     =
==========================================

1998\03\12@190220 by Chris A Brainerd

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Its kinda expensive, but what about SGS-Thomson Zeropower SRAM. Has a 10
year backup battery built in and you don't have to worry about refreshing
it. Just an idea..

       Chris


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I'm, like, a product, OK, of american, you know, education, all right?
.....DJ_RamenKILLspamspam.....juno.com

On Thu, 12 Mar 1998 07:48:18 -0800 Andre Abelian <EraseMEandrespam_OUTspamTakeThisOuTcompufire.com>
writes:
{Quote hidden}

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