Post by thread:DRAM

Hi there oh wealth of knowledge I was very interested in the last DRAM post I got concerning the old 30pin SIMMs. Does any one have the pin outs for them? I gather from looking at it, pin 1 and 30 is ground. I have four 30pin SIMMs with three chips on them and need a bit of a hand identifying the size of this SIMM. The numbers on the chips are: Goldstar GM71C4256AJ80 9221 KOREA I gather that the 256 could mean 256Mbits but who has every hear of a 3/4Mb SIMM

At 09:18 AM 11/10/98 +1300, you wrote: >Goldstar >GM71C4256AJ80 >9221 KOREA This sounds to me like a 256k X 9 bit 80ns SIMM. You would usually put in four of them to get 1MB. (Wow, I still remember doing that on my 386) You could try goldstar's site, I immagine, for more info. Good luck, Sean +-------------------------------+ | Sean Breheny | | Amateur Radio Callsign: KA3YXM| | Electrical Engineering Student| +-------------------------------+ Save lives, please look at http://www.all.org Personal page: http://www.people.cornell.edu/pages/shb7 spam_OUTshb7TakeThisOuTcornell.edu Phone(USA): (607) 253-0315 ICQ #: 3329174

Sean Breheny wrote: {Quote hidden}> > At 09:18 AM 11/10/98 +1300, you wrote: > >Goldstar > >GM71C4256AJ80 > >9221 KOREA > > This sounds to me like a 256k X 9 bit 80ns SIMM. > You would usually put in four of them to get 1MB. (Wow, I still remember > doing that on my 386) > > You could try goldstar's site, I immagine, for more info. > > Good luck, > > Sean > > +-------------------------------+ > | Sean Breheny | > | Amateur Radio Callsign: KA3YXM| > | Electrical Engineering Student| > +-------------------------------+ > Save lives, please look at http://www.all.org > Personal page: http://www.people.cornell.edu/pages/shb7 > .....shb7KILLspam@spam@cornell.edu Phone(USA): (607) 253-0315 ICQ #: 3329174 Agree with Sean here; I have tons of older slower 100 nS 256k SIMMs here someplace, as do most computer techs, you should have no problem finding these. I'm still finding 4-packs of these here & there as I move in <G> Think I have about 1/2 gallon of 256k & 1 Mb SIMMs here total... They can be occasionally found in SIPP packs, a thought for those w/o SIMM sockets, it also would be possible (with ESD protection!) to drill holes through the PC Board & solder in pins in a big hurry, to make these fit a SIP socket. (Make a jig out of 2 little pieces of unetched PC Board, clamp, drill. Handles ESD and drill guiding all in one!) Mark, mwillisKILLspamnwlink.com

Hi Gavin, > concerning the old 30pin SIMMs. Does any one > have the pin outs for them? Here is it. Where have I found it? On the the Hardware Book, a large collection of pinouts: http://www.blackdown.org/~hwb/hwb.html Adriano =========== 30 PIN SIMM Pin Name Description === ==== =========== 1 VCC +5 VDC 2 /CAS Column Address Strobe 3 DQ0 Data 0 4 A0 Address 0 5 A1 Address 1 6 DQ1 Data 1 7 A2 Address 2 8 A3 Address 3 9 GND Ground 10 DQ2 Data 2 11 A4 Address 4 12 A5 Address 5 13 DQ3 Data 3 14 A6 Address 6 15 A7 Address 7 16 DQ4 Data 4 17 A8 Address 8 18 A9 Address 9 19 A10 Address 10 20 DQ5 Data 5 21 /WE Write Enable 22 GND Ground 23 DQ6 Data 6 24 A11 Address 11 25 DQ7 Data 7 26 QP Data Parity Out 27 /RAS Row Address Strobe 28 /CASP Something Parity ???? 29 DP Data Parity In 30 VCC +5 VDC **Note: SIMM above is a 4MBx9. QP & DP is N/C on SIMMs without parity. A9 is N/C on 256kB. A10 is N/C on 256kB & 1MB. A11 is N/C on 256kB, 1MB & 4MB.

On Thu, 11 Feb 1999 20:21:36 +0200 Zack Cilliers <EraseMEzcspam_OUTTakeThisOuTINTEKOM.CO.ZA> writes: >I want to interface DRAM to a pic. I have two questions. >1. To refresh the DRAM can i only address the columns >and the rows will be addressed automatically? Accessing a row will refresh all the columns in that row. To refresh the whole chip, you need to access all the rows within the rated maximum time (usually 4 to 16 ms). DRAMS larger than 256 Kbit and some 256K ones have a mode called "CAS-before-RAS refresh". This mode uses a single pulse to refresh a row. The row address to be refreshed comes from an internal counter dedicated to this purpose, so it is not necessary to supply an anddress to the chip. This mode is usually the best approach to refreshing if you can't set it up so that regular data access will also satisfy the refresh requirement. >2. To read the DRAM must i first latch the column addresses > or the row addresses. First latch the row address using RAS, then the column address using CAS. DRAM's aren't hard to use, but it essential to obtain and carefully study a manufacturer's data sheet. ___________________________________________________________________ You don't need to buy Internet access to use free Internet e-mail. Get completely free e-mail from Juno at http://www.juno.com/getjuno.html or call Juno at (800) 654-JUNO [654-5866]

Mostly because the CPU cannot access the RAM while the refresh is taking place. it's a real timing issue. Alan -----Original Message----- From: Tony Nixon <@spam@Tony.NixonKILLspamENG.MONASH.EDU.AU> To: KILLspamPICLISTKILLspamMITVMA.MIT.EDU <RemoveMEPICLISTTakeThisOuTMITVMA.MIT.EDU> Date: Thursday, February 11, 1999 8:01 PM Subject: Re: DRAM I wonder why they can't make a DRAM chip that has automatic refresh that is transparent to the user. It would seem more practicle. -- Best regards Tony Multimedia 16F84 Beginners PIC Tools. ** NEW PicNPro Programmer and Port Interface ** http://www.picnpoke.com Email spamBeGonepicnpokespamBeGonecdi.com.au

Answers from my memory, which is based on older DRAMs! Donwload a datasheet and study it carefully. > I want to interface DRAM to a pic. I have two questions. > 1. To refresh the DRAM can i only address the columns > and the rows will be addressed automatically? RAS-only refreshing: just apply the Row Address Strobe and all collumn cells are refreshed in parallell, > 2. To read the DRAM must i first latch the column addresses > or the row addresses. Both is possible (RAS-before-CAS or CAS-before-RAS). Watch out for the very high current peeks drawn on refresh (and on normal read, which also counts as refresh). Use ample decoupling! regards, Wouter.

Tony Nixon wrote: I wonder why they can't make a DRAM chip that has automatic refresh that is transparent to the user. It would seem more practicle. its called SRAM. Seriously, because the controller generates the ras, cas, we, etc, its very cheap and easy to do the CBR (cas before ras) refresh. And cost, to add a controller on each chip cost $$, and would have to arbitrate between external control and internal refresh. Think about the problems, if you are reading or writing to a DRAM and the stuff is held off because its doing an internal refresh. You would have to buffer the data, etc.... Harrison Cooper Sr. Hardware Engineer Evans & Sutherland Computer Corp http://www.es.com

At 05:20 AM 2/12/99 -0700, Harrison Cooper wrote: >Tony Nixon wrote: >I wonder why they can't make a DRAM chip that has automatic refresh that >is transparent to the user. > >It would seem more practicle. > > >its called SRAM. Seriously, because the controller generates the ras, cas, Actually, it's called Pseudo-Static Ram. It has been made, but never sold well because the price was outrageous, and nullified any benifits of using the less complex dynamic ram designs. Static ram isn't dram with a controller, it's a whole nother design, with (IIRC) six transistors per cell as opposed to one.

|I wonder why they can't make a DRAM chip that has automatic refresh that |is transparent to the user. |It would seem more practicle. In general, the difficulty is that most memory devices have no way of telling the system when requested data is available. Instead, they simply have a spec which says "data will always be available within XXns of when it's requested". If the chip happened to start an internal refresh cycle just before the system asked for some data, it would take much longer than nor- mal for the chip to supply the data; the only way to provide for that in a normal memory system design would be to slow ALL accesses down to that speed. Note that a somewhat more interesting idea (which was actually discussed in an engineering class I took, and which I'm surp- rised I've not seen done) would be to incorporate multiple row buffers on a DRAM chip and allow them to be accessed under sys- tem control. These extra buffers could be used as a cache, but with a major benefit over normal L2 caching: an entire row buffer may be filled in a single operation. Unfortunately, I'm not aware of any system designs that use this architecture. FYI, a normal DRAM architecture supports four fundamental oper- ations: [1] Read a row from the memory array into the row buffer [note: this will erase the row in the memory array!] [2] Write a row from the row buffer into the memory array. [3] Read out part of the row buffer [send data off-chip] [4] Write part of the row buffer [get data from off-chip] Operation [1] is the slowest (60ns on a 70ns chip); [3] and [4] are the fastest (about 10ns); [2] is in-between (about 30ns). All normal operation of the chip will consist of [1], followed by zero or more occurences of [3] and/or [4], followed by [2]. While a 70ns DRAM can supply the contents of any memory location within 70ns, it can't start another access until 30ns after the previous one is finished (so it can perform step [2]).

---------------------- Note that a somewhat more interesting idea (which was actually discussed in an engineering class I took, and which I'm surp- rised I've not seen done) would be to incorporate multiple row buffers on a DRAM chip and allow them to be accessed under sys- tem control. These extra buffers could be used as a cache, but with a major benefit over normal L2 caching: an entire row buffer may be filled in a single operation. Unfortunately, I'm not aware of any system designs that use this architecture. FYI, a normal DRAM architecture supports four fundamental oper- ations: [1] Read a row from the memory array into the row buffer [note: this will erase the row in the memory array!] [2] Write a row from the row buffer into the memory array. [3] Read out part of the row buffer [send data off-chip] [4] Write part of the row buffer [get data from off-chip] -------------------------- Looks allot like videoRAM, or VRAM. This is basically a DRAM with a static buffer that you can transfer entire rows to, and also write from the buffer back into the DRAM. The buffer is serial, and has some nice features like setting a particular starting address, it can wrap around, etc. Takes 3 states to transfer from the DRAM to the SAM port, and there is stays until you overwrite it. OK, so you say wonderful!! Bad news is the part is basically obsolete. In just 5 years, I went from using a part where I got pre-prod samples from TI and IBM to now it is gone, and we have done our last buys on it. Now I am using SDRAM

|Looks allot like videoRAM, or VRAM. This is basically a DRAM with |a static buffer that you can transfer entire rows to, and also write |from the buffer back into the DRAM. The buffer is serial, and has |some nice features like setting a particular starting address, it |can wrap around, etc. Takes 3 states to transfer from the DRAM |to the SAM port, and there is stays until you overwrite it. True, a VRAM is one type of device which uses more than one row buffer (and a useful one at that); what I (and the prof) was/were thinking of, though, would be a device in which the main processor could access the row buffers 'at will'. In an application which has to move around large amounts of data(*) the ability to get fast access to everything in multiple rows could reap big payoffs. (*) In cases where memory is being moved in row-sized chunks, it would even be possible to read a row into the buffer and write it to multiple rows in the memory array. Of course, given that Windows seems to have a certain sense of ennui which is independent of CPU speed, I'm not sure how much improving the memory infrastructure would help...

what I (and the prof) was/were thinking of, though, would be a device in which the main processor could access the row buffers 'at will'. In an application which has to move around large amounts of data(*) the ability to get fast access to everything in multiple rows could reap big payoffs. Um, All of the assorted "burst mode" capabilities of DRAMs are essentially methods of accessing the row buffer without having to touch the actual RAM array again, right? FPM and EDO for sure? BillW