Post by thread:Context saving during interrupts

I am pondering a predicament. I emulate with the C73 pod on a PicMaster. During interrupts, the W register is saved first. In this case, since RP0 cannot be touched, it can go high or low. Then, when the saved STATUS is restored at the end of the int, the W comes back out from the same place. BUT. I wrote my code to go into a windowed C554. All will fit properly, but I have a problem. This part has only one bank of user RAM. Upon interrupting, I might be in the upper page, and then my W save action will go zinging off into cyberspace. Even if it makes it to the lower page, upon restoring STATUS, it will definitely read zeros when it looks in upper page. Unfortunately, I am using FSR, which is one work around. Double unfortunately, I cannot bracket all high bank reads with disabling ints, as i am interrupting on real fast timing operations. Any grand ideas? Chris Eddy Pioneer Microsystems, Inc.

> BUT. I wrote my code to go into a windowed C554. > All will fit properly, but I have a problem. This part has only one > bank of user RAM. Upon interrupting, I might be in the upper page, and > then my W save action will go zinging off into cyberspace. Even if it > makes it to the lower page, upon restoring STATUS, it will definitely > read zeros when it looks in upper page. The memory architecture on some of those things is--as you have observed--a real pain. It need not be a showstopper, however, as there are some work- arounds. Two that I have seen that may be applicable are: [1] Use the top bit of PCLATH. This will require 3 extra cycles on interrupt entry, and 3 on exit. [2] Use something like this [nb: this uses up an extra stack level] Intr: btfss RP0 goto NotSet bcf RP0 call IntMain bsf RP0 retfie NotSet: call IntMain bsf RP0 retfie IntMain: movwf WSave swapf STATUS,w movwf SSave ... swapf WSave,f swapf SSave,w movwf STATUS swapf WSave,w return ; ** NOT RETFIE! This is a bit clunky, but it should be workable.

On 16 Sep 97 at 21:56, Pioneer Microsystems wrote: > I am pondering a predicament. I emulate with the C73 pod on a > PicMaster. During interrupts, the W register is saved first. In > this case, since RP0 cannot be touched, it can go high or low. > Then, when the saved STATUS is restored at the end of the int, the W > comes back out from the same place. BUT. I wrote my code to go > into a windowed C554. All will fit properly, but I have a problem. > This part has only one bank of user RAM. Upon interrupting, I might > be in the upper page, and then my W save action will go zinging off > into cyberspace. Even if it makes it to the lower page, upon > restoring STATUS, it will definitely read zeros when it looks in > upper page. > > Unfortunately, I am using FSR, which is one work around. > > Double unfortunately, I cannot bracket all high bank reads with > disabling ints, as i am interrupting on real fast timing operations. > > Any grand ideas? How about save RP0 to RP1 (which is unused, but available) set RP0 to 0 (or 1 depending on where your var is) save W to var save whatever else . . do isr . restore whatever else set RP0 to 0 (or 1 depending on where your var is) save var to W save RP1 to RP0 retfie I forgot pclath - handle as per usual, if you're using multiple code pages... MikeS <mikesmith_oz@nosp*m.relaymail.net> (remove the you know what before replying)

On Wed, Sep 17, 1997 at 04:19:31PM +0930, Mike Smith wrote: > On 16 Sep 97 at 21:56, Pioneer Microsystems wrote: > > into a windowed C554. All will fit properly, but I have a problem. > > This part has only one bank of user RAM. Upon interrupting, I might > > be in the upper page, and then my W save action will go zinging off > > How about > save RP0 to RP1 (which is unused, but available) The problem with this solution is that RP1 is marked by Microchip as not to be used - they advise that it should be left at zero. While in the chip itself RP1 does work, and has no bad side effects, if you run the MPLAB simulator for certain chips (not sure if it affects the '554, but it does affect the '62x chips) then setting RP1 does Bad Things. Specifically, all registers become inaccessible, including the STATUS register, so the only way to recover is to reset the simulator. Here's a better solution (or at least one sure to work): this code is what our compiler produces for the '554 interrupts (I've added comments): _isr btfsc 3,5 ;test if RP0 is set goto l30001 movwf saved_w ;if not, bank0 is selected, save w movf 3,w ;load status into w goto l30002 ;rejoin common code l30001 bcf 3,5 ;clear RP0 so we can movwf saved_w ; save W movf 3,w ;get STATUS (with cleared RP0) iorlw 32 ;re-set RP0 in the saved copy l30002 movwf saved_status ;store saved status in memory ;x.c: 6: i++; ; here's your real work incf (_i& (0+127))& (0+127) btfsc 3,2 incf ((_i+1)& (0+127))& (0+127) movf saved_status,w ;now recover saved status andlw 223 ;reset RP0 movwf 3 ;store into STATUS swapf saved_w ;restore W swapf saved_w,w ; using swapf's to preserve STATUS btfsc saved_status,5 ;now test the saved RP0 bsf 3,5 ;set the real RP0 if required retfie ;and continue our regular program... -- Clyde Smith-Stubbs | HI-TECH Software Email: spam_OUTclydeTakeThisOuThtsoft.com | Phone Fax WWW: http://www.htsoft.com/ | USA: (408) 490 2885 (408) 490 2885 PGP: finger .....clydeKILLspam@spam@htsoft.com | AUS: +61 7 3354 2411 +61 7 3354 2422 --------------------------------------------------------------------------- ANSI C for the PIC! Now shipping! See http://www.htsoft.com for more info.

At 09:56 PM 9/16/97 -0400, you wrote: >I am pondering a predicament. I emulate with the C73 pod on a >PicMaster. During interrupts, the W register is saved first. In this >case, since RP0 cannot be touched, it can go high or low. Then, when >the saved STATUS is restored at the end of the int, the W comes back out >from the same place. BUT. I wrote my code to go into a windowed C554. >All will fit properly, but I have a problem. This part has only one >bank of user RAM. Upon interrupting, I might be in the upper page, and >then my W save action will go zinging off into cyberspace. Even if it >makes it to the lower page, upon restoring STATUS, it will definitely >read zeros when it looks in upper page. > >Unfortunately, I am using FSR, which is one work around. > >Double unfortunately, I cannot bracket all high bank reads with >disabling ints, as i am interrupting on real fast timing operations. > >Any grand ideas? This is what I use on that and most other chips. Clyde's is more efficient. org 20h ; Bank 0 RAM Save_W ds 1 ; ISR saves registers here Save_STATUS ds 1 Save_FSR ds 1 <...> org 004h ISR bcf PCLATH,4 btfsc PCLATH,3 ; Copy PCLATH:3 to PCLATH:4 bsf PCLATH,4 bcf PCLATH,3 ; Clear PCLATH so we can jump on Page 0 btfsc RP0 ; Back data bank? goto :Page1Data ; Yes, handle that part movwf Save_W ; Save W swapf STATUS,W ; Save STATUS movwf Save_Status goto :SaveRegs ; Save temp registers :Page1Data bcf RP0 ; Point to data page 0 movwf Save_W ; Save W swapf STATUS,W ; Save STATUS movwf Save_Status bsf Save_Status,1 ; Fix bit in saved copy (works later) :SaveRegs swapf Save_W,F ; Swap for later recall movf FSR,W ; Save FSR movwf Save_FSR ; Insert your registers to save here ; ISR DISPATCHER: ; This routine loops through the interrupt flags in order of precedence ; and calls each routine as required. Looping allows me to minimize ; interrupt latency when multiple interrupts are generated at- or near- ; simultaneously. Each interrupt servicer ends with a "return" ; line to force proper operation. :ISRLoop ; ISRLoop: bcf RP0 btfss TMR1IF ; if (TMR1IF) - TMR1 interrupt goto :Next3 ; { call TMR1_ISR ; tmr1_isr (); goto :ISRLoop ; goto ISRLoop; :Next3 ; } btfss CCP1IF ; if (CCP1IF) - CCP1 interrupt goto :Next4 ; { call CCP1_ISR ; ccp1_isr (); goto :ISRLoop ; goto ISRLoop; :Next4 ; } btfss CCP2IF ; if (CCP2IF) - CCP2 interrupt goto :Next5 ; { call CCP2_ISR ; ccp2_isr (); goto :ISRLoop ; goto ISRLoop; :Next5 ; } bsf RP0 ; if (TXIE) - USART TX enabled? btfss TXIE goto :Next6 bcf RP0 btfss TXIF ; if (TXIF)- USART TX interrupt goto :Next6 ; { call TBE_ISR ; tbe_isr (); goto :ISRLoop ; goto ISRLoop; :Next6 bcf RP0 ; } bsf RP0 ; if (RCIE) - USART RX enabled? btfss RCIE goto :Next7 bcf RP0 btfss RCIF ; if (RCIF)- USART RX interrupt goto :Next7 ; { call RBF_ISR ; rbf_isr (); goto :ISRLoop ; goto ISRLoop; :Next7 bcf RP0 ; } ; btfss INTF ; if (INTF) - INT0 interrupt ; goto :Next1 ; { ; call INT0_ISR ; int0_isr (); ; goto :ISRLoop ; goto ISRLoop; ;:Next1 ; } btfss T0IF ; if (T0IF) - TMR0 interrupt goto :Next2 ; { call TMR0_ISR ; tmr0_isr (); goto :ISRLoop ; goto ISRLoop; :Next2 ; } ; ;---------------------- ; ; Interrupt restore and exit routine movf Save_FSR,W ; Restore FSR movwf FSR ; Insert your registers to restore here swapf Save_Status,W ; Restore STATUS movwf STATUS bcf RP0 ; Point back to BANK0 for grabbing W swapf Save_W,W ; Restore W btfsc Save_Status,1 ; Point back to correct data bank bsf RP0 bcf PCLATH,3 ; Only needed if you LJMP'd off this ban k btfsc PCLATH,4 ; Copy jump bits back in again bsf PCLATH,3 retfie ================================================================== Andy Kunz - Montana Design - 409 S 6th St - Phillipsburg, NJ 08865 Hardware & Software for Industry & R/C Hobbies "Go fast, turn right, and keep the wet side down!" ==================================================================

On 17 Sep 97 at 17:32, Clyde Smith-Stubbs wrote: > On Wed, Sep 17, 1997 at 04:19:31PM +0930, Mike Smith wrote: > > On 16 Sep 97 at 21:56, Pioneer Microsystems wrote: > > > > into a windowed C554. All will fit properly, but I have a problem. > > > This part has only one bank of user RAM. Upon interrupting, I might > > > be in the upper page, and then my W save action will go zinging off > > > > How about > > save RP0 to RP1 (which is unused, but available) > > The problem with this solution is that RP1 is marked by Microchip as > not to be used - they advise that it should be left at zero. While > in the chip itself RP1 does work, and has no bad side effects, if > you run the MPLAB simulator for certain chips (not sure if it > affects the '554, but it does affect the '62x chips) then setting > RP1 does Bad Things. Specifically, all registers become > inaccessible, including the STATUS register, so the only way to > recover is to reset the simulator. Never used the simulator - use an ICE instead... & it works OK on that. - well, it does for the 16c7x series. I wonder why Microchip made their simulator different to the chip? That is bad design (ok using a non-documented feature is too<g>) - like if they suddenly started producing an existing chip on which the TRIS *instruction* (as opposed to registers) didn't work. make a note of your version.... MikeS <mikesmith_oz@nosp*m.relaymail.net> (remove the you know what before replying)

>On Wed, Sep 17, 1997 at 04:19:31PM +0930, Mike Smith wrote: > On 16 Sep 97 at 21:56, Pioneer Microsystems wrote: > into a windowed C554. All will fit properly, but I have a problem. > This part has only one bank of user RAM. Upon interrupting, I might > be in the upper page, and then my W save action will go zinging off This works for me in a '554: INTRTN BCF STATUS,IRP ; Save the Page bit in IRP BTFSC STATUS,RP0 ; not a Microchip approved scheme BSF STATUS,IRP ; BCF STATUS,RP0 ; guarantee page 0 MOVWF WSAVE ; Save W SWAPF STATUS,W ; MOVWF SSAVE ; Save Status ; Balance of the interrupt service routine ; Restore context and return from interrupt SWAPF SSAVE,W ; Restore most of STATUS MOVWF STATUS ; SWAPF WSAVE,F ; Restore W SWAPF WSAVE,W ; BTFSC STATUS,IRP ; Restore the page pointer BSF STATUS,RP0 ; RETFIE ;

On 17 Sep 97 at 10:44, Aydin Yesildirek wrote: > To validate a serial data sequence I was holding the isr measuring > pulse width without ccp option. I might have gotten only one more > int during this time, so didn't worry about stack. > > I don't like to enable gie within isr but it was more intuitive to > program and timings were more accurate. I am not sure whether it can > always be avoided. > Its another case of 'if only it had a proper stack'. Making one in software is much too messy, and, if you have to deal with interrupts, that also will use the stack, you'll need to surround the soft push and pop instructions with gie disable/enaable to make the ops atomic. More jitter. GRRHHH! MikeS <mikesmith_oz@nosp*m.relaymail.net> (remove the you know what before replying)

On Wed, Sep 17, 1997 at 11:08:18PM +0930, Mike Smith wrote: > I wonder why Microchip > made their simulator different to the chip? That is bad design (ok It's a bug. We discovered it because the compiler used to produce the RP0->RP1 save method, but some people complained that with MPLAB (simulator, not emulator) their program would die. The other method is not usable on a PIC with no bank1 RAM, and > 1 page of ROM, but at this time no such chip exists. -- Clyde Smith-Stubbs | HI-TECH Software Email: clydeKILLspamhtsoft.com | Phone Fax WWW: http://www.htsoft.com/ | USA: (408) 490 2885 (408) 490 2885 PGP: finger .....clydeKILLspam.....htsoft.com | AUS: +61 7 3354 2411 +61 7 3354 2422 --------------------------------------------------------------------------- ANSI C for the PIC! Now shipping! See http://www.htsoft.com for more info.

Hi John (John Payson), in <EraseME199709170231.VAA28588spam_OUTTakeThisOuTVenus.mcs.net> on Sep 16 you wrote: {Quote hidden}> [2] Use something like this [nb: this uses up an extra stack level] > > Intr: > btfss RP0 > goto NotSet > bcf RP0 > call IntMain > bsf RP0 > retfie > NotSet: > call IntMain > bsf RP0 > retfie > > IntMain: > movwf WSave > swapf STATUS,w > movwf SSave > ... > swapf WSave,f > swapf SSave,w > movwf STATUS > swapf WSave,w > return ; ** NOT RETFIE! > > This is a bit clunky, but it should be workable. I didn't work with those parts yet, but how about having TWO save registers, at the same position in each bank? Int: movwf WSave ; can be in any bank swapf STATUS,w [switch to bank0] movwf SSave ... swapf SSave,w movwf STATUS ; back to that bank swapf WSave,f swapf WSave,w retfie The WSave location must be reserved in _all_ banks for this to work. Just a thought.