Post by thread:Call for Companies and Master Mode on 73(A)s

Hi Folks, Thanx to everybody that has replied with their companies and such. If you haven't responded yet with your company name, I would appreciate it if you could get it to me as quickly as possible. I also want to thank everybody for replying back to me and not on the list. I will make a finished list available on a Web Site in the next few weeks. PIC Question: I want to hang an I2C Serial EEPROM on a 16C73A and do the data transfer in the background using the interrupt hardware (To allow the maximum possible speed). I think I understand everything in the datasheets (I have done a Serial EEPROM application before, so this is a pretty good guide), but I don't understand how the clock is generated if the PIC is in Master Mode (there is some cryptic references to "Clock Synchronization" in the Datasheets and no reference to generating a clock similarly to that of straight Synchronous Communication). To get this to work, could I wire TMR2 directly to the SCL Pin (Controlling it's Output with the TRIS Bit) and a 200 Ohm - 1K Pull-Down (To ensure the Clock Line goes low when the Clock is made inactive)? This would mean that I have to do my Start/Stop Bits Manually before the I2C h/W is Enabled and after it is disabled. As I said, the reason for doing this is to get the 400 KHz Maximum Data Transfer Speed (I want to be able to read the data out as a constant serial stream). I know this is a pretty deep question, but hopefully, somebody has done it before. myke "I don't do anything that anybody else in good physical condition and unlimited funds couldn't do" - Bruce Wayne