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PICList Thread
'Auto-reset magic?'
1998\10\24@001300 by netquake

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Hello piclisters!

I have a problem. I have a jump to 0000h automagically when reaching value
0x0c of FSR (where is cleared which shouldn't happen).
(FSR increases by one each loop in previous parts of the code)
movf   FSR,W                   ;off-set now in W
       call    table           ;table linear read; off-set stored in W
       movwf   PORTA           ;W now holds fetched table value
                               ;which is put on porta
       bcf     INTCON,INTF     ;just makin'sure everything's chilli willy!
       bsf     INTCON,GIE
       sleep
       nop

table   addwf   PCL,F
       nop                             ;nop added because I need
                                       ;first retlw in table when FSR
                                       ;equals 0x01
       retlw   0x01
       retlw   0x00
       retlw   0x01
       retlw   0x01
       retlw   0x00
       retlw   0x00
       retlw   0x00
       retlw   0x00
       retlw   0x01
       retlw   0x00                    ;I need only bit 0 of each of this bytes
       [some more rets]                ;on port RA0 (linear read).
       nop                             ;But a one byte per bit basis is not
       sleep                           ;a compact code. Any ideas to save space
?
       nop

As it is a simple linear read I must recall (no matter which section of the
code I'm in) the exact bit position that was last read when leaving the
table.
Concerning the reset I have tried a general register instead of FSR and
happen when reg. value equals 0x0c (the same as before) and in the same
part of the code (that is when table off-set is 0x0c and is added to PCL) ,
right before I get
the retlw.
Now 0c plus 3f (initial table position) equals 4B (which is a valid
location in the table)

Thanks.


P.D.: In this code the stack is flooded all the time. I don't need any
return
address. Is this problematic? I also use RB0 as INT to input a clock signal
which
synchronizes the PIC with host device (it must read RA0 output). On falling
edge of
clock signal PIC is interrupted, reads table, put value on RA0 and SLEEP
until
next falling edge (when it wakes up to do the loop again). External clock
signal
on RB0/INT is between 4 and 6 Mhz. Will this do?
Let me know if I wasn't clear enough!

--------------------------------------------
"I must not fear. Fear is the mind-killer.
Fear is the little death that brings total
obliteration. I will face my fear... I will
permit it to pass over me and through me."

Kwisatz Haderach - Dune

       netQ
<spam_OUTnetquakeTakeThisOuTspaminnocent.com>

1998\10\24@042902 by James Cameron

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netQ wrote:
> Let me know if I wasn't clear enough!

Well, um, I did lose track of the precise problem ... but what processor
is it?  Is the table near a page boundary such that you would have to
set the high bits of the PC properly?

Why are you using FSR?  I see no reference to INDF.

--
James Cameron                                    (.....cameronKILLspamspam@spam@stl.dec.com)
Digital Equipment Corporation (Australia) Pty. Ltd. A.C.N. 000 446 800

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