Post by thread:AT Host I/F

> Electronic Mail (via Internet) > Subj: > From: spam_OUTgt5876bTakeThisOuTPRISM.GATECH.EDU (Richard John Farmer) > To: > Sent: Sun, 21 May 1995 23:55:50 -0400 > Rcvd: 21-May-95 21:22:01 (Rcvd by acct: 22-May-95 15:09:43) > > With all the talk of hotrodding pics, which IMHO turns them into say > hc11's, > why not not take a road not traveled? How many of you have had to design > something that had to catch data quickly or do combinatorial logic? By uC > standards a PIC is pretty fast, but it's no match for a PAL/GAL (name your > favorite FPGA). Combine a uC with an FPGA in the same package and you save > tons of interconnects. If the pins were configurable with some extended > version of the now defunct TRIS instruction you would have a winner. > Case in point, I recently built an ISA card and a PIC just isn't fast > enough to catch data off the bus so I had to use a latch. Half my PIC pins > went unused. You don't need anything as fancy as a 22v10, but take a 16cxx > core and extend it to say 48 pins (5 8 bit ports) with a little extra > gating > between the pin and the port, and your close. > > -------------------------------------------------------------------------- > > Rick Farmer .....gt5876bKILLspam@spam@prism.gatech.edu `85 CB700SC AMA# 482666 > 3510 Buford Hwy K-6 85k miles and 10 years of merciless abuse and it > still > Atlanta, Ga. 30329 lives, but then again a spare engine (or two) helps. Rick, This sounds like a perfect application for the "Parallel Slave Port" peripheral in the 40 pin 16Cxx devices, i.e. 16C64 and 16C74. Its not as generic as a PLD peripheral but its great for an 8 bit parallel interface. Just a thought... John E. A. 7:)