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On Tue, 31 Oct 1995, Mikael Lundqvist wrote:
> I'm working on a data aquisition project with a PIC uC involved.
> Does anybody have an idea about if it's possible to attatch
> 512 KBytes of NV- Data Memory to any pic controller and if how
> then how ?? (this sounds stupid!)
> I would be realy glad if somebody has any idea (If 512 is difficult,
> then what about 256,128 or 64KBytes)
Let's see, a Microchip 24C65 (a 64k-bit serial EEPROM) holds 8k-bytes.
Its IIC (2-wire serial) protocol allows for up to 8 such chips on the
same (2-line) serial bus. That's 64k-bytes on just *TWO* uC I/O lines.
If you're willing to throw some supporting hardware on the board, you
can multiplex two lines out to several such banks of 64k-bytes. That
would give you 512k-bytes while only using *FOUR* I/O lines. Nice, eh?
Of course, since it's EEPROM it won't be blindingly fast... but the
data will remain in memory even after your recorder's batteries die.
Oh, it does allow a 64-byte "page write" so it's not bad speed-wise.
Plus, instead of writing data to fill one chip then fill another chip,
you could write a page to each chip in sequence. Then by the time
you get around to the chip again, it's done storing the data. You'd
only need to do that if you have to store lots of data quickly though.
Rick Miller, Design Engineer (and local "Internet Guy")
Digalog Systems, Inc. <digalogsys.com> rick
3180 S. 166th St. <Linux.org> Rick.Miller
New Berlin, WI 53151 USA +1 414 797 8000 x-228
PGP: E1 B8 F3 16 C9 79 5B 07 7C 30 3B 17 E2 C5 B3 47
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> Let's see, a Microchip 24C65 (a 64k-bit serial EEPROM) holds 8k-bytes.
> Its IIC (2-wire serial) protocol allows for up to 8 such chips on the
> same (2-line) serial bus. That's 64k-bytes on just *TWO* uC I/O lines.
> If you're willing to throw some supporting hardware on the board, you
> can multiplex two lines out to several such banks of 64k-bytes. That
> would give you 512k-bytes while only using *FOUR* I/O lines. Nice, eh?
Actually, I think you could do better even without additional support
hardware. Specifically, even with two wires (say PA0 and PA1) you could
drive eight chips with PA0 on SClk and PA1 on SDat and another eight with
PA1 on SClk and PA0 on SDat. You'd have to be careful you didn't acciden-
tally activate the wrong chips, but if you adhere to the right waveforms
that wouldn't happen.
To expand further, with three I/O ports you can drive six banks of chips
and with four I/O ports you can drive twelve banks, two at a time. Of
course, 96 serial EEPROMs would probably cost a few, but the parallel
write facility should allow decent speed.
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