'17C5x async serial I/O'
|I've coded up some interrupt-driven serial-port code for the 17C5x, with
flow control of output, and filled hundreds of screens of MS-Kermit under
Windows 3.11 at 115200bps (with 16550 chips and TurboCom/2 drivers) with no
apparent misses. Although this was mostly output from the PIC, with
keystroke-rate input, I never noticed anything dropped. Not a good test,
just an observation.
But the PIC data book narrative *is* scary: if you look at figure 13-4,
there is indeed no connection from ``START Detect'' to ``Majority Detect'';
in fact, it seems to be the other way around: if the Majority-Detect happens
to find 2 out of three bits down, that will be called a start bit.
Figure 13-7 is reassuringly misleading: it shows samples 7-8-9 being taken
ideally in the middle of the start bit. Whereas in fact, if the narrative
is to be believed, 7-8-9 could just as well have happened where 1-2-3 are
shown, or where 15-16-1 are, etc. In such cases, it seems that a startbit
could be missed, or sampling could fall pathologically on bit boundaries,
rather than bit centers! In this case, just a little DC offset or 1-vs-0
duty cycle asymmetry would produce gobs of errors.
Hey, Microchip, what's all this ``no relationship'' stuff, anyhow?
Peter F. Klammer, Racom Systems Inc. ACM.OrgPKlammer
6080 Greenwood Plaza Boulevard (303)773-7411
Englewood, CO 80111 FAX:(303)771-4708
Is'nt this (from memory) exactly how a 6402 UART works..?
Just get a data sheet for a 6402 and it will show you all the timing
diagrams for a uart.
I've seen things you people wouldn't believe.
Attack ships on fire off the sholder of Orion.
I watched C-beams glitter in the darkness at Tan Hauser Gate.
All those moments will be lost in time,
like tears in rain.
Time to die.
Remember now, watch out for the Fairies......!
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