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'100kHz I2C at 4MHz clock possible'
1997\11\09@212408 by Marc Heuler

Hi Frank (Frank A. Vorstenbosch), in <Marcel-1.29-1030122718-0b0w*> on Oct 30 you wrote:

{Quote hidden}

I have thought about the problem but can't find a reliable solution.  Of
course one can beat the 8 cycles spec you gave, but a _real_ I2C slave
would have to respond to 4.0us events.  The minimum I can reach with RX
checking is 5.0us for start condition loop.

But the original poster wanted an I2C slave without RS232, which can be
done (partially) on a 12C508.

I have not tested the code below but I have counted all cycles and checked
them versus the I2C 100kHz timing specs (tBUF=4.7us, tHD:STA=4.0us,
tHIGH=4.0us, tLOW=4.7us and tSU:DAT=250ns).

It waits for a start condition and tolerates SCL noise while doing so.
After a start condition has been detected it reads a 8 bits into the BUFFER

A STOP condition that follows the START, or occurs during bit reading, is
_not_ recognized.  This might cause incompatibilities!  I have not found a
way to implement it without violating I2C timing.

View it as CONTEST: Add the stop detect without violating the
~~~~~~~~~~~~~~~~~~~ timing specs of I2C.

Maybe one should benefit from 12C508 OSCCAL overclock.  I have measured
>4.8MHz with max OSCCAL value at room temp.  Unfortunately, this does not
necessarily apply to all '508s.

Here's the my code:

#define SCL     PORT,0          ; must be these two pins for 4.0us tHIGH!
#define SDA     PORT,1

Stop    clrf    BUFFER

Noise   btfsc   SCL             ; detects idle state when it lasts for
       btfss        SDA             ; at least 4 cycles (tBUF)
       goto Noise

Idle    btfss   SDA             ; detects start condition when it lasts
       goto Start           ; for at least 4 cycles (tHD:STA)
       btfss        SCL
       goto Noise
       btfsc        SDA
       goto Idle

Start   ; a start condition has occured <=5 cycles ago

       btfsc        SCL             ; wait for first bit
       goto $-1             ; clk must be low at least 3 cycles, lat. 4

       rrf  PORT,w          ; read SDA bit into W.0 from tHIGH=4 cycles
       btfss        STATUS,C        ; SCL was high when sampling?
       goto $-2             ; done by

       andlw        1               ; isolate SDA

       btfsc        SCL             ; tLOW=4 cycles min
       goto $-1

       btfsc        STATUS,Z        ; store SDA
       bsf  BUFFER,0

       rrf  PORT,w          ; wait for & read next bit
       btfss        STATUS,C
       goto $-2
       andlw        1
       btfsc        SCL
       goto $-1
       btfsc        STATUS,Z
       bsf  BUFFER,BITNUM

       RBIT 1
       RBIT 2
       RBIT 3
       RBIT 4
       RBIT 5
       RBIT 6

       rrf  PORT,w          ; wait for & read bit 7
       btfss        STATUS,C
       goto $-2
       andlw        1
       btfsc        STATUS,Z
       bsf  BUFFER,2

ACK is excercise for the reader.

Have fun!

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