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'[slightly OT]: PC RAM: What type is it?'
1998\05\02@135521 by tsk3000

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Hello all,

I was wondering what type of memory is used in PCs.  Is it static or
dynamic RAM?  For instance:  if I went to a local computer store and
bought some generic 72-pin SIMMs, would that memory be static or
dynamic?

I was wondering because is seems to be a cheap alternative to buying
discrete RAM chips... and if it's static, that would make things
much easier for me!

TIA,
--
~Keith
spam_OUTtsk3000TakeThisOuTspamProdigy.Net
http://pages.prodigy.net/tsk3000/

1998\05\02@140559 by Andrew Warren

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flavicon
face
Keith Burzinski <.....tsk3000KILLspamspam@spam@Prodigy.Net> wrote:

> I was wondering what type of memory is used in PCs.  Is it static or
> dynamic RAM?  For instance:  if I went to a local computer store and
> bought some generic 72-pin SIMMs, would that memory be static or
> dynamic?

   Dynamic.  Sorry...

   -Andy

=== Andrew Warren - fastfwdspamKILLspamix.netcom.com
=== Fast Forward Engineering - Vista, California
=== http://www.geocities.com/SiliconValley/2499 (personal)
=== http://www.netcom.com/~fastfwd (business)

1998\05\02@141842 by William Chops Westfield

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   I was wondering what type of memory is used in PCs.  Is it static or
   dynamic RAM?  For instance:  if I went to a local computer store and
   bought some generic 72-pin SIMMs, would that memory be static or
   dynamic?

PC memory simms are all dynamic ram.

Some PC cache chips are relatively normal (but fast) static ram chips, and
have some of the same pricing and availability advantages of dram simms.

BillW

1998\05\02@145333 by tsk3000

picon face
William Chops Westfield wrote:
>
>     I was wondering what type of memory is used in PCs.  Is it static or
>     dynamic RAM?  For instance:  if I went to a local computer store and
>     bought some generic 72-pin SIMMs, would that memory be static or
>     dynamic?
>
> PC memory simms are all dynamic ram.
>
> Some PC cache chips are relatively normal (but fast) static ram chips, and
> have some of the same pricing and availability advantages of dram simms.
>
> BillW
Okay... I was just reading a FAQ file on the MC68000s, the MPU I'm
planning on using. It said:
--
QUESTION
Will the MC68000 support 4 megabytes of DRAM using 1x9 1-Mbyte
SIMMs?


ANSWER
You should have no problems interfacing standard DRAM SIMMs to the
MC68000.Note that the MC68000 does not burst so you do not need any
special
type of DRAM such as page-mode DRAM which would normally be required
to
support bursting.
--
Is this true?  Does this mean that I _can_ just use PC RAM with this
type of MPU?  Does anyone know about or have any experience with
this?

Cheers,
--
~Keith
.....tsk3000KILLspamspam.....Prodigy.Net
http://pages.prodigy.net/tsk3000/

1998\05\02@153657 by William Chops Westfield

face picon face
       QUESTION
       Will the MC68000 support 4 megabytes of DRAM using 1x9 1-Mbyte SIMMs?

       ANSWER

       You should have no problems interfacing standard DRAM SIMMs to the
       MC68000.Note that the MC68000 does not burst so you do not need any
       special type of DRAM such as page-mode DRAM which would normally be
       required to support bursting.

   Is this true?  Does this mean that I _can_ just use PC RAM with this
   type of MPU?  Does anyone know about or have any experience with this?

Sure, you CAN.  You'll need some sort of DRAM controller to at least
multiplex the address bus into the DRAM pins, unless you're using some 68k
variant that has a built-in DRAM controller.  How hard it is may depend on
how fast you want the system to go - if you clock the DRAM signals in based
on the 68k clock, you'll probably end up with a longer access cycle than
strictly necessary.  Using a separate clock gets you synchronization
issues, of course.  Some designs use delay lines here, I think.

The other thing that DRAM needs is periodic refresh - on low end systems,
you can use "software refresh".  Rather than complicating your memory
controller, you set up a periodic non-maskable interrupt to occur at the
refresh frequency, and then do a full columns worth of reads (ie 128
consecutive no-ops, assuming you put the right address lines in the right
place.)  Both the SUN-1 and cisco CSC/1 were 68k based processors that used
SW refresh.  IIRC, the original IBMPC used a periodic interrupt to start
an appropriately sized DMA (to nowhere) using the DMA controller.  Your
periodic interrupt routine can do more than no-ops, of course, as long
as it always reads something from every DRAM row...

BillW

1998\05\02@195142 by Mike Keitz

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On Sat, 2 May 1998 12:35:20 PDT William Chops Westfield <EraseMEbillwspam_OUTspamTakeThisOuTCISCO.COM>
writes:

>>    Is this true?  Does this mean that I _can_ just use PC RAM with
>>this
>>    type of MPU?  Does anyone know about or have any experience with
>>this?

First decide if you really need the megabytes that DRAM offers.  The
smaller the memory size, the more attractive SRAM becomes.  A one-MB
array of two 512K x 8 SRAMs is probably a good break point for small
productions.  If cost is real important, then use DRAM earlier and accept
the complexity.

One way would be to build a developmental version using SRAM.  When the
software is more complete, it can be migrated to a less-costly "final"
version using DRAM.  Then the complexities of running DRAM and writing
software to use megabytes of space don't occur at the same time.

>Sure, you CAN.  You'll need some sort of DRAM controller to at least
>multiplex the address bus into the DRAM pins, unless you're using some
>68k
>variant that has a built-in DRAM controller.

Some processors, maybe even some in the 68000 line, have built-in DRAM
control.  Just make a direct connection to the DRAM and set up a few
registers.  The AMD 29000 line comes to mind.  These were intended to
"power" laser printers, which of course need lots of memory.  Imagine a
32-bit AVR chip, with an actual 30 MHz rating...

How hard it is may
>depend on
>how fast you want the system to go - if you clock the DRAM signals in
>based
>on the 68k clock, you'll probably end up with a longer access cycle
>than
>strictly necessary.  Using a separate clock gets you synchronization
>issues, of course.

If using a state-machine type of DRAM controller, definitely divide down
the CPU clock from the state clock so it is certain to be in sync.

>Some designs use delay lines here, I think.

A once-popular design used 74S158 chips, a tapped delay line, and a
little more TTL or a PAL.  As the "memory request" signal traveled
through the delay line, it would activate the DRAM in proper sequence:
RAS, change address, CAS, WR.

>The other thing that DRAM needs is periodic refresh - on low end
>systems,
>you can use "software refresh".
...

This is very practical.  Other than the relatively long idle time to
execute a burst refresh, the performance really isn't degraded that much.
With some applications, such as a DSP or communications buffer, a
specific refresh action may be completely unnecessary.  The data can be
arranged in RAM so that normal operation is certain to read or write all
the rows in the DRAM often enough.

If you have more than one 'bank' of DRAM, for example using a 32-bit wide
72-pin SIMM as two banks of 16 bits, you have to refresh both banks.  One
way is to RAS all the chips all the time, then only CAS the ones in the
bank in use.  This will refresh all chips by doing enough (usually 512)
consecutive reads in either bank.  But in normal operation, half of the
DRAMs will be activated unnecessarily so the circuit will use more power.
A little more logic in the control circuit so the "refresh reads" RAS
all chips but normal reads don't may be useful.

>  IIRC, the original IBMPC used a periodic interrupt to
>start
>an appropriately sized DMA (to nowhere) using the DMA controller.

It worked about that way.  One of the timer channels would, at about a 62
KHz rate, hit the DMA controller for a DMA cycle.  The CPU wasn't
involved other than giving up the bus for the DMA cycle.  It was a 1 byte
read of a different address each time.  The DMA cycle wouldn't actually
read anything, but it would activate special circuitry to RAS all the
DRAMs (4 banks of 64K in the more popular "256K" model).

I think this method persists into modern PC's, but of course it is now
buried in the VLSI support chips on the main board.


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