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'[pic]:16f872'
2001\07\16@131856 by Jim Kane

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Hello folks;
1)  Why is the duty register 10 bits when the pr is 8?  It seems that
whenever either upper bit is set in duty, the output will be 100%.
2)  I am using tmr0 int.  In the isr a register is decremented, if it isn't
at 0, a retfie is executed, if it is at 0 a goto is made.  Is this a
generally accepted technique?

Thanks
Jim

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2001\07\17@201159 by Dan Michaels

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Jim Kane wrote:
>Hello folks;
>1)  Why is the duty register 10 bits when the pr is 8?  It seems that
>whenever either upper bit is set in duty, the output will be 100%.
>2)  I am using tmr0 int.  In the isr a register is decremented, if it isn't
>at 0, a retfie is executed, if it is at 0 a goto is made.  Is this a
>generally accepted technique?
>


Jim,

1 - For PWM duty cycle, bits 4/5 of CCPxCON are concatenated to
the low end of CCPRxL to get a full 10-bits, while the period uses
only the 8-bits of PR2. If bits 4/5 are just left as 0's, you
use the CCPRxL register alone for 8-bit duty cycle.

2 - It's unclear from your description, but normally you do not
want to < goto > "out of" the ISR, but you can branch around inside.
In normal ops, you leave the ISR only via retfie.

Regarding executing retfie, you cannot of course simply do it,
but need to do all of the correct register saves and restores
on entering and exiting the ISR - as described in the PIC
datasheets - else the cpu will crash.

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2001\07\18@131840 by Jim Kane

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Dan:
Thanks for the comments.
1)I'm aware of the constitution of the 10 bits of duty, but my question is
why?  If the period reg is 8 bits, any set of bits 9 and 10 at any time will
yield 100%.  Do I have that right?
2) In the retfie I do save via MC's published method the status and W regs.
When I goto out of the isr, I won't need the hardware stack contents (I hope
that's right), but maybe I should restore the registers.  The application is
too long to describe here.  Thanks.  JIm

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2001\07\19@005357 by Bob Ammerman

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> Dan:
> Thanks for the comments.
> 1)I'm aware of the constitution of the 10 bits of duty, but my question is
> why?  If the period reg is 8 bits, any set of bits 9 and 10 at any time
will
> yield 100%.  Do I have that right?

No: because bits 9 and 10 are really bits -1 and -2. What I mean by that is
that they are the least significant bits of the duty cycle, and can be
considered fractional bits relative to the resultion of the period.

This is because each count in the period register actually maps to 4 clock
cycles (one instruction cycle). The extra PWM bits let you resolve to the
individual clock cycle.


Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

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2001\07\19@110609 by Dan Michaels

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James Kane wrote:
>Dan:
>Thanks for the comments.
>1)I'm aware of the constitution of the 10 bits of duty, but my question is
>why?  If the period reg is 8 bits, any set of bits 9 and 10 at any time will
>yield 100%.  Do I have that right?

No, as I said last time, the 9th and 10th bits concatenate on the "LSB" end.
================

>2) In the retfie I do save via MC's published method the status and W regs.
>When I goto out of the isr, I won't need the hardware stack contents (I hope
>that's right), but maybe I should restore the registers.  The application is
>too long to describe here.  Thanks.  JIm
>

Details are too sketchy to understand exactly what your problem is here.
Normally you don't goto out of an ISR, you exit it via retfie, using
proper bookkeeping procedures - register retores. OTOH, some people
[myself included] use interrupts to break out of endless loops/etc,
and go back to the starting/initialization point in the code.

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2001\07\19@135927 by Jim Kane

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A dim light begins to flicker.  Thanks Bob.
Jim

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