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'[pic]: Timer0 problem'
2001\04\21@100528 by pang khong lin

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Hi everyone,

Need some help on the source code below. Basically i need to implement
a counter using the Timer0. I am using a 16F84A and i disabled the
watchdog. I am assigning the ratio 1:256 for the prescaler and
i am using additional 2 counters.

; source codes

MAIN    < some operation >

       bank1
       bsf     OPTREG,RBPU
       bsf     OPTREG,INTEDG
       bcf     INTCON,INTF
       bsf     INTCON,INTE
       bsf     INTCON,GIE

LOOP    sleep           ; let IRQ wake it up and determine functions
       nop
       clrwdt              ; initialisation of Timer0
       bank1
       bcf     OPTREG,PSA
       bcf     OPTREG,TOCS
       bsf     OPTREG,PS2
       bsf     OPTREG,PS1
       bsf     OPTREG,PS0

       goto    DATA_RECEIVE

FINISH  goto    LOOP    ; go back to sleep and wait for the next INT


DATA_RECEIVE
       clrf    timer2
       clrf    timer3
DV_HIGH bank0
       btfss   PORTB,DV   ; TEST FOR THE DV ( / Data Valid )
       goto    DV_LOW     ; if Low, then Data Valid True, branch out

       btfss   INTCON,TOIF     ; if not,check if TMRO overflow
       goto    DV_HIGH         ; no overflow, check DV again
       bcf     INTCON,TOIF     ; got overflow, reset the TOIF
       incf    timer2          ; increment timer2 counter
       btfss   STATUS,C        ; check if timer2 overflow
       goto    DV_HIGH         ; timer2 no overflow, check DV again
       clrf    timer2          ; timer2 overflow, reset timer2
       incf    timer3          ; increment timer3 counter
       movf    timer3,W
       sublw   H'0A'           ;
       btfss   STATUS,Z        ; check for timer3 = 10
       goto    DV_HIGH      ; timer3 less than 10, continue check DV
       goto    LOOP            ; timer3 = 10, stop checking DV
                               ; go back sleep


The accuracy of the time is not important. and based on a rough calculation
the duration that i can wait for DV ( Data Valid ) to go LOW is around

time for TMRO to overflow

(1 / 2.5MHz) x 256 x 255 = 0.02611 sec

time for timer2 to overflow

0.02611 sec x 255 = 6.658 sec

time for timer3 to overflow ( the whole duration )

6.658 sec x 10 = 66.58 sec

What i am trying to do is to have a counter so that if the DV
does not goes LOW after around 1 min. , i stop polling for DV
and return to sleep. actually the DV is some sort of user response.
is there anything wrong with my code? One last question, can i just simply
reset the TMR0 flag as and when i like it? and when the overflow occurs, the
timer will still continue running right?

Thanks for reading.


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2001\04\21@112205 by michael brown

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face
> Hi everyone,
>
> Need some help on the source code below. Basically i need to implement
> a counter using the Timer0. I am using a 16F84A and i disabled the
> watchdog. I am assigning the ratio 1:256 for the prescaler and
> i am using additional 2 counters.
>
> ; source codes
>
> MAIN    < some operation >
>
>         bank1
>         bsf     OPTREG,RBPU
>         bsf     OPTREG,INTEDG

          Shouldn't you be switching back to bank0 here????  INTCON is in
bank0

>         bcf     INTCON,INTF
>         bsf     INTCON,INTE
>         bsf     INTCON,GIE
>
> LOOP    sleep           ; let IRQ wake it up and determine functions

Hope this helps

mike

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2001\04\21@113048 by michael brown

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Oops. I just checked the datasheet and I told a big lie :-(  Sorry about
that. This is what I get for trying to help.



{Quote hidden}

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2001\04\21@180721 by Olin Lathrop

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> Shouldn't you be switching back to bank0 here????  INTCON is in
> bank0

INTCON is mapped to the same location in all banks.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, EraseMEolinspam_OUTspamTakeThisOuTembedinc.com, http://www.embedinc.com

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2001\04\23@090121 by pang khong lin

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Hi, i am sorry that i repost that mail. It will be the last time. Can anyone
point out any error? Thanks.


{Quote hidden}

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2001\04\24@045157 by Vasile Surducan

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On Mon, 23 Apr 2001, pang khong lin wrote:

{Quote hidden}

is not need a bank0 here ?

{Quote hidden}

I'm not sure, but it might be a bank switching problem, timer2 and timer3
in DATA_RECEIVE are in bank1 and in DV_HIGH in bank0...


One last question, can i just simply
> >reset the TMR0 flag as and when i like it?

yes, but you don't need to do that only if tmr0_if is set

and when the overflow occurs,
> >the timer will still continue running right?

yes

Vasile

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