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'[ot]: game boy camera'
2002\11\27@141815 by Rad R. Rad

picon face
hello,

I am trying to write a program for the game boy camera chip,
there are several web sites that explain how to do this, but
I need remedial help

If any of you can help to decipher the data sheet for the
image processor chip, I would be greatly appreciative.

http://www.lh.co.nz/hardware/ar/techinfo.htm

html site with the datasheet

I've never tried to communicate with a chip like this and I'm
stuck.

I'm doing this with a stamp for the time being, and I'm pretty
much confused between the description of how it describes how to
do a reset, for example, and between what the timing diagrams show
that you need to do.

for example in the reset, the data sheet tells you that 'the reset
sequence completes when both the Xrst and RESET signals are set low.'

This seems to be saying that you hold both of these signals low, and
this will reset the chip.

However, the timing diagram shows the Xrst and RESET signals as
begining high, then going low, with the clock (Xck) signal pulsing
above, then the Xrst and RESET resuming high again.

So, in other words it shows that the Xrst And RESET signals just need
to be pulsed low, to get a reset.

Which is it?  Am I getting wound up over the way this thing is worded?  Do
you most usually 'pulse' these type of signals?  And I'm not sure if
you have to send a pulse to the RESET pins while you clock the clock.

Any help is greatly appreciated.  Eventually, after I try everything each
possible way, I'll get this thing to work.  But your help would speed
me along.


thanks in advance

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2002\11\27@173600 by Jinx

face picon face
> much confused between the description of how it describes how to
> do a reset, for example, and between what the timing diagrams show
> that you need to do.

Timing diagrams don't always show what happens in the real circuit
(over a long period for example). They are meant to show the timing
relationships between signals. See (10) AC Timing Requirements
as well as the timing diagram. Also (11) Operation

> for example in the reset, the data sheet tells you that 'the reset
> sequence completes when both the Xrst and RESET signals
> are set low.'
>
> This seems to be saying that you hold both of these signals low, and
> this will reset the chip.

Yes, same as sending MCLR low resets a PIC, but you don't leave it
low or the PIC would be in permanent reset and wouldn't do nuttin'

> However, the timing diagram shows the Xrst and RESET signals as
> begining high, then going low, with the clock (Xck) signal pulsing
> above, then the Xrst and RESET resuming high again.
>
> So, in other words it shows that the Xrst And RESET signals just need
> to be pulsed low, to get a reset.

Sounds about right. The Xck is there to show timing / setup as per (10)

Don't expect to do much on-the-fly image processing with a Stamp BTW.
A bare micro with no interpreter overhead is much much faster

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2002\11\27@182507 by Rad R. Rad

picon face
>
> Timing diagrams don't always show what happens in the real circuit
> (over a long period for example). They are meant to show the timing
> relationships between signals. See (10) AC Timing Requirements
> as well as the timing diagram. Also (11) Operation

jinx - I think you are saving me here...

On (10) it says the MAX Xck rise time is 0.2 uS
(that's MAX)

my stamp cannot do this,
(I don't think??)

if I'm understanding this at all,

I guess I better get out the pic (877) or whatever is needed
(I always have trouble getting the higher Mhz oscillators to
function - at all)

So far, circuit wise, I have only set up a stamp with an ADC 831
analog to digital, I don't think this is fast enough to even begin
to try to get an image from this image chip...

I'll get a better A/D and set up the pic with picBasic

Let me know if I'm screwing the pooch here....thanks

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2002\11\27@195848 by Jinx

face picon face
> On (10) it says the MAX Xck rise time is 0.2 uS
> (that's MAX)
>
> my stamp cannot do this,
> (I don't think??)

At the pin itself the rise/fall time probably is that fast, but
generating a 500kHz clock signal is a different matter

> I guess I better get out the pic (877) or whatever is needed
> (I always have trouble getting the higher Mhz oscillators to
> function - at all)

You have several options for getting Xck

1) 500kHz ceramic resonator + a few gates

2) use a 20MHz crystal for the PIC and divide it down in hardware
to get 500kHz. 20MHz for a PIC is pretty routine (for a properly
rated part of course), you shouldn't have any trouble

Tap off the 20MHz from OSC1 or OSC2 with a high impedance
gate and run it through division h/w as discussed the other day
( "[OT]:Need to divide frequency by 163" ). The aim is produce
a 500kHz Xck with > 800ns hi/lo times as per (10).

3) A 20MHz PIC may just be able to generate a 500kHz clock via
TMR0 IRQ at 50% duty cycle. However, the ISR would be coming
every 5 clock cycles (2 ISRs per Hz - one for high, one for low) so

4) use one (small/cheap) PIC dedicated to making the 500kHz at
whatever mark/space ratio is passable by simple instruction cycle
usage between pin toggles and another PIC for everything else. I
haven't tried to work it out but you should be able to write a toggling
routine that takes 10 cycles at 20MHz = 500kHz output

5) 555 timer

> Let me know if I'm screwing the pooch here....thanks

Please, my reputation for salacious comments is already well
established ;-) I have no further need to enhance it

(BTW, if some of you guys are in the "doghouse", what does
that make the house where your missus is ? Starts with "b")

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2002\11\27@204624 by Justin Grimm

flavicon
face
I ran this off a pic16c74 a few years ago, can't remember the details
though. If you like tonight I can find the circuit etc and see how I did it.

Justin

{Original Message removed}

2002\11\28@090805 by Bob Ammerman

picon face
A 20Mhz PIC can generate a 500KHz clock via its PWM output.

Set period to 10 (ie set PR2 to 9)

Set duty cycle to 5

And you've got 500KHz, symmetrical.

Bob Ammerman
RAm Systems


{Original Message removed}

2002\11\29@115335 by Dave Tweed

face
flavicon
face
Did anyone respond to this yet? The bad tag may have had something to do
with it.

"Rad R. Rad" <EraseMErad0spam_OUTspamTakeThisOuTATTBI.COM> wrote:
{Quote hidden}

It appears that two areas of the chip ("system" and "parameter memory") can
be reset independently.

Both reset inputs are synchronous; if either one is low when a rising edge
of the clock occurs, the corresponding area will get reset. If you want to
reset the entire chip, you can pull both resets low on the same clock edge,
as shown in their timing diagram.

You're probably getting confused because most chips have asynchronous reset
inputs, which don't need a clock.

-- Dave Tweed

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