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'[TECH]Challenge for the FPGA users here.'
2011\01\08@032530 by cdb

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Universities of Glasgow and Massachusetts, have made a pseudo equivalent 1K core CPU using FPGA's

http://tinyurl.com/2whkto3

http://www.gla.ac.uk/

Colin
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2011\01\08@034955 by Sean Breheny

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Interesting...I wish they had said which FPGA they used. I'm used to
working with smaller ones (equivalent to maybe 100k gates) where even
a single simple microcontroller "core" would take up something like
1/4 of the FPGA.

I did do one cool learning exercise, though, where I made a (if I
recall correctly) 24 bit by 16 bit integer divide unit which could
give the result in a single clock cycle of up to 80MHz. It took up
half the chip, though :)

Sean


On Sat, Jan 8, 2011 at 3:25 AM, cdb <.....colinKILLspamspam@spam@btech-online.co.uk> wrote:
{Quote hidden}

>

2011\01\08@072438 by Oli Glaser

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On 08/01/2011 08:49, Sean Breheny wrote:
> Interesting...I wish they had said which FPGA they used. I'm used to
> working with smaller ones (equivalent to maybe 100k gates) where even
> a single simple microcontroller "core" would take up something like
> 1/4 of the FPGA.

I wondered which FGPA too - the fact they did not mention it stood out for me, I reckon it was probably one of the latest offerings (xM gates) and likely well over £3000 per unit (the price of a 2M gate FPGA on Mouser is  ~£4000 GBP) Might have made the story a little less "exciting" to mention this kind of thing.. :-)
To do some (very) simple (and rough) math, the smallest core I have used takes around 30k gates (I think) Say even if this was reduced to 10k, then 10k * 1000 = 10M gates. Even with lots of clever resource sharing it would hard to achieve less than say 5M gates, plus all the onboard RAM each core needs which is mentioned. Quite probable it could be some (as yet not on the market) technology in excess of £10k.
Certainly interesting though, and the above technology will not be that expensive for too long, would like to know a bit more.

2011\01\08@120152 by M.L.

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On Sat, Jan 8, 2011 at 3:49 AM, Sean Breheny <.....shb7KILLspamspam.....cornell.edu> wrote:
> Interesting...I wish they had said which FPGA they used. I'm used to
> working with smaller ones (equivalent to maybe 100k gates) where even
> a single simple microcontroller "core" would take up something like
> 1/4 of the FPGA.
>
> I did do one cool learning exercise, though, where I made a (if I
> recall correctly) 24 bit by 16 bit integer divide unit which could
> give the result in a single clock cycle of up to 80MHz. It took up
> half the chip, though :)
>
> Sean
>
>

They likely used something like this:
http://www.dinigroup.com/

It doesn't seem logical to fit any meaningfully useful number of
soft-cores on a single FPGA. Unless they have some wafer-scale part..
unlikely.

-- Martin K

2011\01\08@121617 by N. T.

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cdb wrote:
>  Universities of Glasgow and Massachusetts, have made a pseudo equivalent
> 1K core CPU using FPGA's

The point was not about the number 1000, I think. Because, say, NVIDIA
GTX 580 GPU has got 512 cores already (besides the other stuff
on-board). And, most probably, they could allocate a lot more if they
wanted to. I can imagine what the main idea is about, but I am not
sure of the idea.

NVIDIA® GeForce® GTX 580 GPU:
www.nvidia.com/object/product-geforce-gtx-580-us.html
GPU Engine Specs:
CUDA Cores        512
Graphics Clock (MHz)        772 MHz
Processor Clock (MHz)        1544 MHz

2011\01\08@131003 by Oli Glaser

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On 08/01/2011 17:01, M.L. wrote:
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It does say "on a single chip" though. To have done it on one of those > 30M gate multi-FPGA boards would be "easy" and far less impressive I guess.
I think the cores they are not your typical soft cores we are used to, probably designed/specialised to work together at the task in hand, share resources etc (probably a bit like the cores on GPUs as N.T notes) Maybe they are stretching the definition of the word "core" (e.g. does it have a "full" instruction set? can it perform "standard" core tasks? etc)
It would be nice to know more (sure we will soon), like how adaptable it is - they only mention one thing they did with it, with no details of how easy it was to "set up" for that task, what else it could do and so on. Does raise a few questions about how you you would go about developing for something like this, although parallel/multithreaded development has been around for a while, surely some new techniques would be required if the number of cores were to rise so drastically very quickly (similar to the new techniques needed to deal with such large FPGAs)

2011\01\08@150223 by N. T.

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Oli Glaser wrote:
> It does say "on a single chip" though. To have done it on one of those >
> 30M gate multi-FPGA boards would be "easy" and far less impressive I guess.
> I think the cores they are not your typical soft cores we are used to,
> probably designed/specialised to work together at the task in hand,
> share resources etc (probably a bit like the cores on GPUs as N.T notes)
> Maybe they are stretching the definition of the word "core" (e.g. does
> it have a "full" instruction set? can it perform "standard" core tasks? etc)
> It would be nice to know more (sure we will soon),

They are investing hundreds of millions in the idea (concept), and I'm
sure they know what they are doing.  Good ideas are not always cheap

2011\01\08@154327 by Sean Breheny

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Where did you see that they are investing such money in the concept? I
thought this was being done by teams at two universities - I've never
heard of a university-based research project costing more than a few
10s of millions.

Sean


On Sat, Jan 8, 2011 at 3:02 PM, N. T. <ntypesemispamspam_OUTgmail.com> wrote:
{Quote hidden}

>

2011\01\08@171241 by smplx

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On Sat, 8 Jan 2011, N. T. wrote:

{Quote hidden}

When I first read Colin's post I wondered just how complex each core was and it reminded me of the old ICL DAP. I don't know much about the DAP except what I had heard (many many years ago) that it was a matrix of single bit processors :-)

I just looked it up and wikipedia says it "had 64x64 single bit processing elements"

Regards
Sergio Masci

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2011\01\08@171813 by jim

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30M is just a few 10's of M

-----Original Message-----
From: @spam@piclist-bouncesKILLspamspammit.edu [KILLspampiclist-bouncesKILLspamspammit.edu] On Behalf Of
Sean Breheny
Sent: Saturday, January 08, 2011 2:43 PM
To: Microcontroller discussion list - Public.
Subject: Re: [TECH]Challenge for the FPGA users here.

Where did you see that they are investing such money in the concept? I
thought this was being done by teams at two universities - I've never
heard of a university-based research project costing more than a few
10s of millions.

Sean


On Sat, Jan 8, 2011 at 3:02 PM, N. T. <RemoveMEntypesemiTakeThisOuTspamgmail.com> wrote:
> Oli Glaser wrote:
>> It does say "on a single chip" though. To have done it on one of those >
>> 30M gate multi-FPGA boards would be "easy" and far less impressive I
guess.
>> I think the cores they are not your typical soft cores we are used to,
>> probably designed/specialised to work together at the task in hand,
>> share resources etc (probably a bit like the cores on GPUs as N.T notes)
>> Maybe they are stretching the definition of the word "core" (e.g. does
>> it have a "full" instruction set? can it perform "standard" core tasks?
etc)
>> It would be nice to know more (sure we will soon),
>
> They are investing hundreds of millions in the idea (concept), and I'm
> sure they know what they are doing.  Good ideas are not always cheap.
>

2011\01\08@173455 by Oli Glaser

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On 08/01/2011 20:02, N. T. wrote:
> Oli Glaser wrote:
>> It does say "on a single chip" though. To have done it on one of those>
>> 30M gate multi-FPGA boards would be "easy" and far less impressive I guess.
>> I think the cores they are not your typical soft cores we are used to,
>> probably designed/specialised to work together at the task in hand,
>> share resources etc (probably a bit like the cores on GPUs as N.T notes)
>> Maybe they are stretching the definition of the word "core" (e.g. does
>> it have a "full" instruction set? can it perform "standard" core tasks? etc)
>> It would be nice to know more (sure we will soon),
> They are investing hundreds of millions in the idea (concept), and I'm
> sure they know what they are doing.  Good ideas are not always cheap.

Like Sean, I can't see any mention either of how much funding there is behind this.
Just in case I'm misunderstood, I wasn't criticising their efforts at all (not anywhere near enough info to make any judgement) just speculating...
I'm sure they know what they are doing too, it all sounds very impressive....

P.S.  Ideas are free - it's the application/realisation of them (or the extraction of them from whoever had them, persuading them to have more etc..) that may not be.. :-)

2011\01\08@174225 by cdb

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Looks as though it will be a case of 'watch this space' until March, when Dr Vanderbauwhede gives his talk to the Applied Reconfigurable Computing meeting.

I wonder how many organisations that represents.

Colin
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2011\01\08@182436 by William \Chops\ Westfield

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On Jan 8, 2011, at 9:01 AM, M.L. wrote:

> It doesn't seem logical to fit any meaningfully useful number of
> soft-cores on a single FPGA.

The article has the marks of one of those "stories" where what the  researchers think they accomplished and what ends up in the press are  pretty far apart.

“This is very early proof-of-concept work where we’re trying to  demonstrate a convenient way to program FPGAs so that their potential  to provide very fast processing power could be used much more widely  in future computing and electronics."

This article in eetimes is a bit more enlightening:
www.eetimes.com/electronics-news/4211856/1-000-processors-on-a-Xilinx-FPGA
Note the reference to reconfigurable computing; I think this has more  to do with creating a 1000-core specialized-algorithm device "on the  fly" than implementing a general purpose 1000-core CPU.

BillW

2011\01\08@204653 by Sean Breheny

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Yes, but the 30M figure applies to the number of gates. The poster
ntypesemi said "investing hundreds of millions" presumably of US
dollars.

Sean


On Sat, Jan 8, 2011 at 5:18 PM, jim <TakeThisOuTjimEraseMEspamspam_OUTjpes.com> wrote:
> 30M is just a few 10's of M
>
> {Original Message removed}

2011\01\09@040136 by N. T.

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William "Chops" Westfield <RemoveMEwestfwspamTakeThisOuTmac.com> wrote:
> “This is very early proof-of-concept work where we’re trying to
> demonstrate a convenient way to program FPGAs so that their potential
> to provide very fast processing power could be used much more widely
> in future computing and electronics."
>
> This article in eetimes is a bit more enlightening:
> www.eetimes.com/electronics-news/4211856/1-000-processors-on-a-Xilinx-FPGA
> Note the reference to reconfigurable computing; I think this has more
> to do with creating a 1000-core specialized-algorithm device "on the
> fly" than implementing a general purpose 1000-core CPU.

Yes, they wrote:
"...efficiency over traditional architectures via customizing, even at
runtime, the topology of the underlying architecture to match the
specific needs of a given application."

But, let me guess, they target Speedster 22i FPGAs as well, not only
Xilinx's FPGAs.
There were no a press release by Intel, there was only a blog post on the deal:
A Minute On Manufacturing Access
http://blogs.intel.com/technology/2010/10/

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