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'[Serial I\O (was Re: TMR0 Latency]]'
1999\10\22@204507 by Stephen Holland

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Anytime the RTCC register is written to, the prescaler register (internal -
not the prescaler ratio) is cleared.

BTW, the 2 additional 16-bit timers and larger RAM (262 bytes) of the SX48/52
might help your application.

Stephen

Thomas Brandon <spam_OUTtomTakeThisOuTspamPSY.UNSW.EDU.AU> wrote:
> Yep, this and the hardware context saves for interrupts make the Scenix a
> dream for this task. Having 10X more instructions doesn't make it any
harder
> either. Also, the versatile port configuration helps. On the PIC I could
> only have interrupt on change (actually, I wasn't going to use this as the
> time to determine interrupt source was a problem, better done through my
own
> polling) whereas I can have selectable edge sensing on all the Port B pins
> on a Scenix. Yep, the scenix is the way to go for this. I have ordered the
> Parallax SX Tech Kit to this end.
>
> The application is MIDI which is 31250bps. I will prob. either run 16X (100
> inst\bit) or 8X clock as in hardware UARTs (16X) and simply sample at the
> middle of each bit. This will increase the number of interrupts but
decrease
{Quote hidden}

to
> sync. to the next start bit. But MIDI has no hardware flow control. So If a
> device is only giving 1bit (exactly) stop bits, how can you determine
what's
{Quote hidden}

> {Original Message removed}

1999\10\24@212254 by Thomas Brandon

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Thanks for clarifying that. Could have had a lot of problems. I'm thinking
I'll use the mov w, -100; retiw  sequence recommended by parallax with no
prescaler. This seems pretty easy and modifiable. The only problem is if the
interupt handler takes more than 97 (or so) inst. I could miss a cycle. If
this is a problem, I can simply test for a new cycle at the end of the
interrupt, but I can't see this being a problem. I will do start bit
detection via the Falling edge detection circuitry, however, I will simply
poll the edge detect bits rather than using interrupts as edge detects are
not time critical (they just log a cycle for checking on) and this will
eliminate interrupt source checking.

Certainly the extra RAM of the 48\52 would be lovely, I would like to have
more than the 136bytes RAM (I wish Scenix would release a couple of 18\28
DIP chips with more than 136bytes RAM) but the SMD only thing is a bit of a
problem. Hopefully I can get by on 8 (4IN, 4OUT) 8byte FIFO's. With 50MIPS I
shouldn't have stuff sitting in FIFO's for too long as long as the other end
can keep up.

I've started writing the input, and it seems pretty easy. I am working with
1 16X (100 inst) loop as in hardware UARTs. Ocassionaly this might short
cycle the background loop (if all 4 ins, end a byte on the same cycle, the
background loop won't get much time). But this can only happen a maximum of
once every 160 cycles so shouldn't be a problem.

Tom.
----- Original Message -----
From: Stephen Holland <.....stephen.hollandKILLspamspam@spam@USA.NET>
> Subject: Re: [Serial I\O (was Re: TMR0 Latency]]


> Anytime the RTCC register is written to, the prescaler register
(internal -
> not the prescaler ratio) is cleared.
> BTW, the 2 additional 16-bit timers and larger RAM (262 bytes) of the
> SX48/52 might help your application.
> Stephen

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