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'[PICLIST] pulses with 1-cycle resolution'
2002\04\24@130238 by Bob Blick

face picon face
Hi Friends,

I'm wanting to generate pulses on a pin with 1 cycle resolution. This
routine I'm using does OK for 8 bit values, and can even be easily
modified for 10 bit values. I'd like to expand it to 16 bits, but
everything I do looks ugly.

I don't care about overhead or setup - the timing before and after the
pulse is not critical, but the width of the pulse is.

Here's my 8 bit routine:

       bsf     PORTA,0 ;set the pin high
       bcf     3,0     ;clear carry
       rrf     count   ;rotate right
       btfss   3,0     ;test bit 0, take long way if set
       goto    $+2
       nop
       bcf     3,0     ;same thing again
       rrf     count
       btfss   3,0     ;long way is longer for bit 1
       goto    $+4
       nop
       nop
       nop
       decfsz  count   ;4-cycle loop the rest
       goto    $-2
       bcf     PORTA,0

Any takers?

Cheerful regards,

Bob Blick

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2002\04\24@133621 by Dmitriy A. Kiryashov

picon face
Hi Bob.

What do you mean 1 cycle resolution?
Is it 4 clocks(commands) ?

WBR Dmitry.


{Quote hidden}

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2002\04\24@141117 by Bob Blick

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On Wed, 24 Apr 2002, Dmitriy A. Kiryashov wrote:
> What do you mean 1 cycle resolution?
> Is it 4 clocks(commands) ?

Hi Dmitriy,
1 cycle meaning 1 microsecond with 4 MHZ crystal.

Cheerful regards,

Bob

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2002\04\24@145917 by Bob Blick

face picon face
This is what I came up with for a 16 bit pulse on RA0. It has 1 execution
cycle resolution and simulates OK, I haven't calculated the overhead but
it seems to be the same regardless of what number is fed to it:

       bsf     PORTA,0 ;set pin high
do_high:               ;high byte sets the number of 256 cycle delays
       movf    countHI,f
       btfsc   3,2     ;test for zero
       goto    do_low
       movlw   0x53    ;this constant makes it 256 cycle delay
       movwf   temp
       decfsz  temp
       goto    $-1
       decf    countHI
       goto    do_high
do_low:                ;finish up with the low byte
       bcf     3,0     ;clear carry
       rrf     countLO ;rotate right
       btfss   3,0     ;test LSB, take long way if set
       goto    $+2
       nop
       bcf     3,0     ;same thing again
       rrf     countLO
       btfss   3,0     ;except long way is even longer
       goto    $+4
       nop
       nop
       nop
       decfsz  countLO ;4-cycle loop the rest
       goto    $-2
       bcf     PORTA,0 ;clear the pin
Cheerful regards,

Bob

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2002\04\24@165355 by Scott Dattalo

face
flavicon
face
On Wed, 24 Apr 2002, Bob Blick wrote:

> This is what I came up with for a 16 bit pulse on RA0. It has 1 execution
> cycle resolution and simulates OK, I haven't calculated the overhead but
> it seems to be the same regardless of what number is fed to it:


How about:

 ; divide the counter by 16

  swap  countHI,f
  swap  countLO,w

  movwf countLO
  andlw 0xf0
  movwf temp
  xorwf countLO,f

  movwf countHi,W
  andlw 0xf0
  xorwf countHI,F
  iorwf countLO,F

 ; 16-cycles per loop iteration
l1
  goto   l2
l2
  call   delay13
  decfsz countLO,F
   goto  l1
  decfsz countHI,F
   goto  l2

 ; delay table - or you could check the low four bits
 ; as shown below

  movf   temp,W
  sublw  0x0f
  addwf  pcl,f

  nop
  nop
  nop
  nop
  nop
  nop
  nop
  nop

  nop
  nop
  nop
  nop
  nop
  nop
  nop
  bcf    porta,0

  return

delay13
  call   delay4
delay9:
  call   delay4
delay5
  nop
delay4
  return

Looks like about 16 cycles of over head.


Another variation similar to your solution can be found in:

http://www.dattalo.com/technical/software/pic/pwm256.txt

Look specifically at the "end_pulse" routine. (Actually, there several
phase delay tricks in this code.)

For example, here's a portion of it that will give you 5-bit
single-cycle resolution pulse with 11 cycles of overhead.

       BTFSC   pw,4            ;01;01;
        CALL   delay17         ;02;02
ep1     BTFSC   pw,3            ;03;19
        CALL   delay9          ;04;20
       BTFSC   pw,2            ;05;29
        CALL   delay5          ;06;30
ep2     BTFSS   pw,1            ;07;35
        goto   $+3             ;08;36
       NOP                     ;  ;37
       GOTO    $+1             ;  ;38
ep3     BTFSS   pw,0            ;10;40
        BCF    PWM             ;11;sk
       BCF     PWM             ;12;42

Turning this into a 4-bit delay is straight forward.

There are also tricks like this:

    movf   countLO,w
    sublw  0x8
    andlw  7
    addwf

    bsf    porta,0
    bsf    porta,0
    bsf    porta,0
    bsf    porta,0

    bsf    porta,0
    bsf    porta,0
    bsf    porta,0
    bsf    porta,0


This will create a phase-shifted startiing edge.


Scott

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2002\04\24@192220 by Bob Blick

face picon face
oop, made a little mistake in do_low. This fixes it and gives a cosistent
18-cycle overhead:

       bsf     PORTA,0 ;set pin high
do_high:               ;high byte sets the number of 256 cycle delays
       movf    countHI,f
       btfsc   3,2     ;test for zero
       goto    do_low
       movlw   0x53    ;this constant makes it 256 cycle delay
       movwf   temp
       decfsz  temp
       goto    $-1
       decf    countHI
       goto    do_high
do_low:                ;finish up with the low byte
       bcf     3,0     ;clear carry
       rrf     countLO ;rotate right
       btfss   3,0     ;test LSB, take long way if set
       goto    $+3
       nop
       nop
       bcf     3,0     ;same thing again
       rrf     countLO
       btfss   3,0     ;except long way is even longer
       goto    $+4
       nop
       nop
       nop
       decfsz  countLO ;4-cycle loop the rest
       goto    $-2
       bcf     PORTA,0 ;clear the pin

Cheerful regards,

Bob Blick

On Wed, 24 Apr 2002, Bob Blick wrote:

{Quote hidden}

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2002\04\24@193710 by Bob Blick

face picon face
Hi Scott!

On Wed, 24 Apr 2002, Scott Dattalo wrote:

>   ; delay table - or you could check the low four bits
>   ; as shown below
>
>    movf   temp,W
>    sublw  0x0f
>    addwf  pcl,f
>
>    nop
>    nop

Yes, I thought about that, but since I'm putting the assembler inline with
C it would take someone smarter than me to figure out how to do it safely.
Likely it'd cross a page boundary and I'd be falling in midair.

> delay13
>    call   delay4
> delay9:
>    call   delay4
> delay5
>    nop
> delay4
>    return

Yes, this is the kind of thing I was hoping for, keep it coming...


> Another variation similar to your solution can be found in:
>
> http://www.dattalo.com/technical/software/pic/pwm256.txt
>
> Look specifically at the "end_pulse" routine. (Actually, there several
> phase delay tricks in this code.)

several is an understatement - where's that can of Pepsi I was guzzling?

{Quote hidden}

Nice.




{Quote hidden}

This I am not following. How do jump into this nest of bsf's?

Thanks!

Best regards,

Bob

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2002\04\24@201028 by Scott Dattalo

face
flavicon
face
On Wed, 24 Apr 2002, Bob Blick wrote:

> > Look specifically at the "end_pulse" routine. (Actually, there several
> > phase delay tricks in this code.)
>
> several is an understatement - where's that can of Pepsi I was guzzling?

It wouldn't hurt to mix a little something with it :).

> > There are also tricks like this:
> >
> >      movf   countLO,w
> >      sublw  0x8
> >      andlw  7
> >      addwf

should be
        addwf  PCL,f

{Quote hidden}

Oops. You can't as it was written. I forgot to type the PCL,f  as part of
the addwf instruction... But after looking at it for a few seconds, I see
that even with the "addwf  pcl,f" instruction there's a bug the code
should read:


    movf   countLO,w
    andlw  7
    sublw  0x8
    addwf  PCL,f

    bsf    porta,0
    bsf    porta,0
    bsf    porta,0
    bsf    porta,0

    bsf    porta,0
    bsf    porta,0
    bsf    porta,0
    bsf    porta,0

The idea is that the lower three bits of countLO define the entry into the
table. Suppose the lower 3-bits are all zero. 8-0 = 8 and you jump to the
last bsf instruction. If the lower 3-bits are say 101=5, then 8-5 = 3 and
you jump to the third bsf instruction. Of course, you'll execute the 4'th,
5'th, .. bsf's, but you can't over bsf an I/O!

Scott

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2002\04\25@145705 by Peter L. Peres

picon face
He means things like:

 bsf   Fout,Bout       ; pulse starts after this instr.

 movlw PULSE_LENGTH    ; T = 14 + 4*(PULSE_LENGTH-1) [Tcyc]
 movwf Ftemp

 btfsc Ftemp,0
 goto  ($+1)
 btfss Ftemp,1
 goto  ($+3)
 nop
 goto  ($+1)

 rrf   Ftemp,f
 rrf   Ftemp,f
 bcf   Ftemp,7

loop:
 nop
 decfsz Ftemp,f
 goto loop

 bcf   Fout,Bout       ; pulse ends after this instr.

I am sure that SOMEONE will shave a few cycles off ;-). Untested code.

Peter

------

On Wed, 24 Apr 2002, Dmitriy A. Kiryashov wrote:
> What do you mean 1 cycle resolution?
> Is it 4 clocks(commands) ?

Hi Dmitriy,
1 cycle meaning 1 microsecond with 4 MHZ crystal.

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2002\04\26@125952 by Wagner

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> Subject: Re: pulses with 1-cycle resolution
> From: Bob Blick (.....bblickKILLspamspam.....SONIC.NET)
> Date: Wed Apr 24 2002 - 11:08:48 PDT

>> On Wed, 24 Apr 2002, Dmitriy A. Kiryashov wrote:
>> What do you mean 1 cycle resolution?
>> Is it 4 clocks(commands) ?

> Hi Dmitriy,
> 1 cycle meaning 1 microsecond with 4 MHZ crystal.
>
> Cheerful regards,
>
> Bob

What about a 100 ns pulse width at a port pin using 10 MHz crystal?  try an AVR.

What about a 20 ns pulse using 50 MHz crystal? try the new Dallas 89C420 (8051
family).

Wagner Lipnharski
http://www.ustr.net
Orlando - Florida

(PS: if this is a learning experience, lets learn it right. According to I.S.
the letter "z" in MHz should be lowercase)

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2002\04\26@140930 by Dwayne Reid

flavicon
face
At 10:00 AM 4/24/02 -0700, Bob Blick wrote:
>Hi Friends,
>
>I'm wanting to generate pulses on a pin with 1 cycle resolution. This
>routine I'm using does OK for 8 bit values, and can even be easily
>modified for 10 bit values. I'd like to expand it to 16 bits, but
>everything I do looks ugly.

The following is a re-post of something that Mike Harrison, myself, and
Nikolai Golovchenko worked out a couple of years back.  Sorry for the
length but it may contain something useful for your application.

From:         Nikolai Golovchenko <golovchenkospamspam_OUTMAIL.RU>

<snip>
> ;10 bit delay routine providing 1 cycle resolution.  Works with both 12 &
> 14 bit core PICs.
> ;Original idea from Mike Harrison.  This version by Dwayne Reid
> ;
> ;enters with upper 8 bits of delay in DELAYU, lower 2 bits in bits 1,0 of
> DELAYL
> ;bits 7..2 in DELAYL can be used as flags for whatever purpose desired.
> ;returns with W destroyed
> Delay10bit      ;delay is 10 bit value + 7 cycles ( + call + return, if any)
>      incf        DELAYU,F        ;correct for dec & test instead of test
& dec
> Dly10bLoop
>      comf        DELAYL,W        ;invert LSBs
>      decfsz      DELAYU,F
>        goto      Dly10bLoop      ;coarse delay to closest 4 cycles
>      andlw       b'00000011'
>      addwf       PCL,F
>      nop
>      nop
>      nop

> I hope one of these is useful.

> dwayne
<snip>

Dwayne, this is a nice one!

Let's now extend it to ANY delay :)

;-----------------------------------------------------------
;d0, d1, d2, ...dn      - counters
;d0 = 0..3              - least significant 2 bits
;d1,...dn = 0..255      - more significant 8, 16, 24, ... bits
;
;Total Delay =
;= d0+4*d1+4*256*d2+4*256*256*d3...+4*256^(n-1)*dn + overhead
;
;Overhead depends on a number of counters, see below

;First preincrement all counters except d0
;overhead = n cycles
        incf d1, f
        incf d2, f
        ...
        incf dn, f
;2 bit delay (d0 - 1 cycle resolution)
;overhead += 4 cycles
        comf d0, w
        andlw 0x03
        addwf PCL, f
Delay64Mx
Delay256Kx
        nop
Delay1Kx
        nop
Delay4x
        nop
;8 bit delay (d1 - 4 cycle resolution)
;overhead += 2 cycles
        decfsz d1, f
         goto Delay4x

;8 bit delay (d2 - 1024 cycle resolution)
;overhead += 3 cycles
        decf d1, f
        ;change d1 to 255, so previous loop
        ;(from Delay4x) will take
        ;255*4-1=1019 cycles
        ;we need to add 5 more cycles to get 1024.
        ;4 cycles are in this loop and
        ;another 1 cycle is a nop above

        decfsz d2, f
         goto Delay1Kx

;8 bit delay (d3 - 262144 cycle resolution)
;overhead += 3 cycles
        decf d2, f
        ;previous two loops (from Delay4x) will take
        ;1019+255*1024-1=262138 cycles
        ;we need to add 6 more cycles to get 262144.
        ;4 cycles are in this loop and
        ;another 2 cycles are above - two nops

        decfsz d3, f
         goto Delay256Kx

;8 bit delay (d4 - 262144*256 cycle resolution)
;overhead += 4 cycles
        decf d3, f
        ;previous two loops (from Delay4x) will take
        ;262138+255*262144-1 cycles
        ;we need to add 7 more cycles to get 4*256^3.
        ;5 cycles are in this loop and
        ;another 2 cycles are above - two nops
        nop
        decfsz d4, f
         goto Delay64Mx

;at this point we have a 34 bit one cycle resolution delay!
;Total Delay = overhead + 0..1.7e10 cycles
;overhead = 4+4+2+3+3+4 = 20 cycles
;-----------------------------------------------------------




Dwayne Reid   <@spam@dwaynerKILLspamspamplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax

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