> http://www.ednmag.com/reg/1996/071896/15di7.htm
>
> Your delay line consists of an inverter, series R, C
> to ground,
> 2nd invertor (schmidt if you want really clean
> edges) to the
> other leg of the XOR.
>
> Cascade two of them to get a 4x pulse train, then
> divide by 2
> to get your symetric output. Your RC delay should be
> about 1/4 period
> for your highest frequency. You don't need to worry
> about the lower
> frequencies since you're only generating pulses on
> the edges of the
> input waveforms. If it works at 8Mhz, it will work
> find at 740Khz.
> I recommend 74HC14 since the thresholds won't shift
> much with
> temperature and so your delay will be quite
> consistant (or you
> can use the silicon delays of the above article).
>
>
>

> What frequency is it that you are doubling?
> Is is sinewave or square? TTL or CMOS or something
> else?
> Does the doubled waveform have to be symetric?
>
> If it's square and TTLish you can make a simple
> double by using
> a XOR gate (74HC14) and a set of invertors
> (perferably schmidt).
>
> You basically feed the main signal to one side of
> the
>  XOR, and a delayed copy (muliple inverters with an
> RC delay
> of 1/2 Tau) to the other side. You get a decent
> doubled signal
> out. If you repeat the process and then divide by 2
> with a
> flip flp, you get a perfect 2X square wave out, and
> if you need
> a sinewave you add a tuned circuit (or low pass
> filter) to
> remove the higher harmonics.
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>

> It's the mismatch between your HC buffers and the
> LS86
> that is partly causing your problem. The output will
> not be
> symetric with your choices, but it WILL be EXACT if
> you've chosen
> 'reasonable' values for the R/C delay. If your
> values are inappropriate,
> the tresholds will not be crossed cleaning and so it
> is possible to to
> have 'inexact' doubling.
>
> And you probably have insufficient/excessive delay.
> The delay should be 1/4 the period of the input
> signal (1/2 of the width
> of the pulse high or low time) for the frequency
> supplied to each stage. This means DIFFERENT delays
> for the cascaded
> stages.
>
> And you failed to use schmidt trigger buffers so the
> delay leg output
> may be 'mushy' (unsquare).
>
> The HC buffers typically  have a threshold that is
> 1/2 VCC (2.5V),
> while the LS86 threshold is 0.6V. This low threshold
> will obviously
> cause your transitions to happen too early on the
> rising edge, and
> too late on the falling making a symetrical multiply
> difficult to
> achieve with a 74LS86.
>
> I also said that the doubling would be "decent", as
> in 'approximate'.
> For most applications where one is clocking
> something, and so only
> ONE edge is important, this simple circuit is
> sufficient. Tuning the
> value
> of the R/C can get you very close to a square wave.
>
> Since the output of your first stage is not very
> symetric, I doubt
> that the output of your 2nd stage is doubled at all.
> If you used a schmidt trigger buffer (as
> recommended) your circuit
> would be more likely to work since cascading relies
> on having at least
> one
> FAST rising edge (so the output is square), and I
> rather doubt that the
> output of your first multiplier stage is square
> using LS244s.
> You may also have made inappropriate choices for the
> R/C delay (needed
> when
> using low (<1Mhz) frequencies.
>
> You really need to look at this circuit with a scope
> to select
> components
> that will work with the devices you've chosen. You
> didn't mention what
> values of R & C you used for your delay.
>
> With the recommended components, (74HC14 and
> 74HC86),  I have no problem
> doubling 1Mhz to 2 with R=100, C=100pF.
>
> You can also get away from R/C by cascading many
> (2-8) of your HC244
> stages
> for the delay leg since each stage adds about 10ns
> delay.
>
> This is a very simple circuit that works well, IF
> appropriate devices
> & components are used.
>
> Robert
>
>
> Jane Ifurung wrote:
> >
> > Mr. Robert, I tried the frequency doubler you
> > suggested and I've got a fair output. The thing
> is,
> > it's not very exact and it's not symmetric. I used
> > HC244 buffers for the delay and 74LS86 XOR. To
> solve
> > for the duty cycle, I tried to cascade two
> frequency
> > doubler and connect it to divide-by-two flip-flop.
> But
> > the problem is, the output goes back to the input
> > frequency. I checked my connections and nothing's
> > wrong. Is there a loading effect? Is there a
> mismatch
> > between the HC and LS? I tried using LS244 and
> LS86
> > but the problem is still the same.
> >
> > --- Robert Rolf <KILLspamRobert.RolfKILLspamUALBERTA.CA> wrote:
> > > What frequency is it that you are doubling?
> > > Is is sinewave or square? TTL or CMOS or
> something
> > > else?
> > > Does the doubled waveform have to be symetric?
> > >
> > > If it's square and TTLish you can make a simple
> > > double by using
> > > a XOR gate (74HC86) and a set of invertors
> > > (perferably schmidt like 74HC14).
> > >
> > > You basically feed the main signal to one side
> of
> > > the
> > >  XOR, and a delayed copy (muliple inverters with
> an
> > > RC delay
> > > of 1/2 Tau) to the other side. You get a decent
> > > doubled signal
> > > out. If you repeat the process and then divide
> by 2
> > > with a
> > > flip flp, you get a perfect 2X square wave out,
> and
> > > if you need
> > > a sinewave you add a tuned circuit (or low pass
> > > filter) to
> > > remove the higher harmonics.
> > > >
> __________________________________________________
>
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>
>

> jane:
> >for the duty cycle, I tried to cascade two
> frequency
> >doubler and connect it to divide-by-two flip-flop.
> But
> >the problem is, the output goes back to the input
> >frequency.
>
> you may find that making the two RC networks
> different will fix this.
> try halving the R in one of the networks for
> example.
>
> (reasoning: if the two networks are _exactly_ the
> same then you just end up with pulses that are
> twice as wide after the second network... of course
> in real life the two networks will not be quite
> identical even with the same nominal value
> components, this will give a glitch as wide as the
> difference between the two networks in the center of
> the stretched pulse. this glitch may or may not
> be too fast for the flip-flop to see it.)
>
> Simon
>
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>

> Hi,
>
> I've got a variable frequency signal (200hz to 4khz) whose frequency I want
> to increase by 30% (5v signal).  IE if the input frequency is 1000hz, I
> want to output 1300hz.  Is there an easy method of doing this?  I've heard
> of PLL, but don't have a clue how to build them, so if there's an easier
> option that would be great.
>
> Thanks,
>
> Gary

> Great, very simple, very good.
>
> Bill
>
> ----- Original Message -----
> From: "Rychta Bretislav"
> <EraseMEBretislavRychta@spam@ALVISHAGGLUNDS.SE>
> To: <@spam@PICLISTspam_OUT.....MITVMA.MIT.EDU>
> Sent: Monday, April 28, 2003 11:48 PM
> Subject: SV: [PIC]: Frequency multiplier?
>
>
> The better way is to add 10 to input count and
> subtract 13 from output
> count. When output count underflow, toggle output
> pulse and ADD 'last pulse
> count' to output count.
> This approach don't need any further correction
> and allow you to easy change
> ratio of input and output frequency by changing
> only 2 constants.
> Run sequence on interrupt from timer to get
> constant sampling frequency
> which is in your case higher than 2*4000*13/10 Hz
> and lower than 2*200*65536/10 Hz (for 2-Byte
> counters)
>
> Breta
>
> -----Ursprungligt meddelande-----
> Fren: Bill & Pookie
> [spamBeGonewilliamcornutt111EraseMEATTBI.COM]
> Skickat: mendag 28 april 2003 16:05
> Till: PICLISTspamBeGoneMITVMA.MIT.EDU
> Dmne: Re: [PIC]: Frequency multiplier?
>
>
> Looking at the question as inputting a signal with
> a 50% duty cycle and outputting a signal 130%
> greater with a 50% duty cycle, here is my
> solution.
>
> Requires 4 routines,
>
> count input pulse width
> see if input changed
> decrement output count
> see if time to change output
>
>
> COUNT INPUT PULSE WIDTH
>
> In order to get the increase in frequency, the
> input count must be reduced before it becomes the
> count for the output.  This is done by not
> counting the input pulse every forth time.
>
> The 'fourth input counter' will add a count to the
> input count to 'tweak it from 125% to 130% every
> 13th time it is called.  The 52 (4*13) input
> timings results in 39 (3*13) input counts, and if
> 1 input count is added at this time, the
> percentage of 40 counts to 52 timings is 130%.
>
> SEE IF INPUT CHANGES
>
> When the input state changes, the input count is
> moved to the 'last pulse count' and the input
> pulse count is cleared. It may be a good idea to
> average the last pulse count and input pulse
> instead of just moving it.  This is easily done by
> adding the two and right shifting the results.
> This averaging will encourage a 50% duty cycle for
> the output pulses.
>
> DECREMENT OUTPUT COUNT
>
> Just subtract one from output count.
>
> SEE IF TIME TO CHANGE OUTPUT
>
> if output count is zero, toggle output pulse and
> move 'last pulse count' to output count
>
> So there would be three series of
> count input pulse width
> see if input changed
> decrement output count
> see if time to change output
>
> And a fourth series with the 'count input pulse
> width' modified to only counting every 13th time.
>
> One main concept is that the input pulse and
> output pulse have no relationship in time except
> the 'last pulse count', and that count can change
> any time with the output routine using it when it
> toggles the output pulse and starts a new pulse.
>
> Bill
>
>
> ----- Original Message -----
> From: "Gary Neal" <RemoveMEgln103@spam@spamBeGonePSU.EDU>
> To: <.....PICLIST@spam@EraseMEMITVMA.MIT.EDU>
> Sent: Wednesday, April 23, 2003 6:08 PM
> Subject: [PIC]: Frequency multiplier?
>
>
> > Hi,
> >
> > I've got a variable frequency signal (200hz to
> 4khz) whose frequency I want
> > to increase by 30% (5v signal).  IE if the input
> frequency is 1000hz, I
> > want to output 1300hz.  Is there an easy method
> of doing this?  I've heard
> > of PLL, but don't have a clue how to build them,
> so if there's an easier
> > option that would be great.
> >
> > Thanks,
> >
> > Gary
> >
> > --
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>

> Thanks to all for your answers to my 50% stuff question.
> I perhaps didn't explain myself properly or didn't understand your answer
> correctly.
> Let me please rephrase my question. Let's say I want to multiply the
> frequency of an input square wave by some factor "F".Consider a sensor
> giving pulses from a rotating shaft, if the shaft accelerates then two
> consecutive periods are different. Every next period will be shorter than
> the previous one. Now if I divide the first period "P" by "F" and output an
> "F" amount of pulses with periods equal to "P/F" then the PIC will still be
> outputting pulses while the next period is already happening. I can't loose
> counts since I need this for positioning, direction and speed measurement
> purposes. I have to watch both edges for any change in the direction of the
> shaft.The sensor is a quadrature encoder with only A and B outputs, no Z. I
> have to output two channels out of phase by ~90% to the system processing
> the data.The phase difference is naturally the same as the incoming pulse.
> I have managed to do it for a fixed or slow variable frequency.I
> implemented it in software on an 16F84A, I know they are outdated, but I
> have lots of them!. When the shaft accelerates fast then I start to miss
> about 3 to 10% of the pulses depending on the acceleration, getting offsets
> in
> position.When the shaft is slowing down then is ok because the next period
> will be longer. There will be space enough in time to accommodate the
> multiplied pulses before the next ones will have to be outputted. I might
> be missing something here, I don't know what a phase accumulator is but
> I'll try to find out. It looks to me that this task is just not possible to
> fix on a base of period by period multiplication. I appreciate very much
> any advise or pointer to how to solve this. And sorry for taking this
> thread, I didn't mean to.
> Best regards
> RA

> -----Original Message-----
> From: Reinaldo Alvares [SMTP:RemoveMEreinaldoalvaresspam_OUTTELIA.COM]
> Sent: Wednesday, April 30, 2003 9:22 AM
> To:   PICLISTspamMITVMA.MIT.EDU
> Subject:      Re: [PIC]: Frequency multiplier?
> No is not an x-y plotter.The encoder is on a moving cart with a scanning
> system on it. The pulses are used to trigger one scan per pulse. The
> encoder
> is connected to the shaft of one of the wheels. I used magnets placed on
> the
> wheel to trigger an Allegro hall effect sensor with quadrature output.
> Because of the size of the wheel I could not mount more magnets on it. I
> used the smallest ones I could found 1mm diameter. The magnets were used
> because this equipment goes into water, dust and many other tough
> conditions, where optical systems are difficult to implement. So the end
> was
> to get an E4 encoder from USdigital and get a rugged case for it. The
> whole
> construction is a cylinder 120mm long and 29mm diameter and solved all the
> problems. I spent quite a while trying to do the trick with a micro,
> that's
> why I was interested in some opinions regarding this. I guess from the
> beginning it was a doomed project. Anyway, I always try to listen to other
> people because one can never learn to much.
> Thanks a lot for your time.
>

> Thanks to all for your answers to my 50% stuff question.
> I perhaps didn't explain myself properly or didn't understand your answer
> correctly.
> Let me please rephrase my question. Let's say I want to multiply the
> frequency of an input square wave by some factor "F".Consider a sensor
> giving pulses from a rotating shaft, if the shaft accelerates then two
> consecutive periods are different. Every next period will be shorter than
> the previous one. Now if I divide the first period "P" by "F" and output an
> "F" amount of pulses with periods equal to "P/F" then the PIC will still be
> outputting pulses while the next period is already happening. I can't loose
> counts since I need this for positioning, direction and speed measurement
> purposes. I have to watch both edges for any change in the direction of the
> shaft.The sensor is a quadrature encoder with only A and B outputs, no Z. I
> have to output two channels out of phase by ~90% to the system processing
> the data.The phase difference is naturally the same as the incoming pulse. I
> have managed to do it for a fixed or slow variable frequency.I implemented
> it in software on an 16F84A, I know they are outdated, but I have lots of
> them!. When the shaft accelerates fast then I start to miss about 3 to 10%
> of the pulses depending on the acceleration, getting offsets in
> position.When the shaft is slowing down then is ok because the next period
> will be longer. There will be space enough in time to accommodate the
> multiplied pulses before the next ones will have to be outputted. I might be
> missing something here, I don't know what a phase accumulator is but I'll
> try to find out. It looks to me that this task is just not possible to fix
> on a base of period by period multiplication. I appreciate very much any
> advise or pointer to how to solve this. And sorry for taking this thread, I
> didn't mean to.