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'[PICLIST] PIC: Use of SS in slave mode.'
I am using a 16C63 as an SPI slave (with SS* enabled).
When doing multi-byte transfers, does the SS* pin need to be cycled (by
the master) after each byte, or can it remain low for the entire
Galen O'Grady C.E.T.
Research & Development
Reliable Scale Corporation
520 Moraine Road N.E.
Calgary, AB, Canada T2A 2P2
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|> I am using a 16C63 as an SPI slave (with SS* enabled).
> When doing multi-byte transfers, does the SS* pin need to be cycled (by
> the master) after each byte, or can it remain low for the entire
> Galen O'Grady C.E.T.
> Research & Development
No. You do not need to cycle it between each byte transfer. To wit, to
test this notion, setup your SPI in slave mode with SS control enabled, and
ground the SS line. The SPI will function identically, provided you are
transferring 8 bits per word (as you implied when you described the data as
Recently, I was having an issue with my SPI Slave code. I had SS control
enabled. However, it seems that the device sourcing the SS signal was not
conforming to the timing requirements for the PIC. Merely grounding the SS
line allowed the SPI subsystem to function properly. Subsequently, I
configured my SPI to not use SS control.
The PICmicro Mid-Range MCU Family manual says this:
"When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> =
0100) the SPI
module will reset if the SS pin is set to VDD. If the SPI is used in Slave
Mode with the CKE bit is
set, then the SS pin control must be enabled.
When the SPI module resets, the bit counter is forced to 0. This can be done
by either by forcing
the SS pin to a high level or clearing the SSPEN bit..." (c) Microchip
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